Stacking the Odds: Full-Stack Quantum System Design Space Exploration

2025-06-03

AI Summary

Quantum circuit fidelity is severely degraded by hardware noise, topology constraints, and compilation choices; yet the coupled impact of compiler strategies (qubit mapping, routing, optimization level) and hardware parameters (noise spectrum, connectivity, scale) remains poorly quantified. Method: We propose a noise-aware full-stack design space exploration (DSE) framework integrating Qiskit-based compilation modeling, hardware sensitivity analysis, fidelity prediction, and quantum error correction (QEC)-aware simulation. Contribution/Results: Our work is the first to quantitatively demonstrate that judicious selection of initial qubit layout and routing can suppress hardware errors more effectively than conventional error mitigation techniques. We further establish that hardware–software co-design remains critical even in QEC-enabled scenarios. Experiments across diverse noisy intermediate-scale quantum (NISQ) and prospective fault-tolerant architectures show an average 12.7% improvement in expected fidelity, alongside reductions in circuit depth and gate count. The framework delivers actionable mapping strategies and hardware configuration guidelines for both near-term noisy and future fault-tolerant quantum systems.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Learning to Search
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Responsible Web: Human-perceived consequences of algorithmic deployment on the web
• Security and Privacy: Large-scale security measurements

Abstract

Design space exploration (DSE) plays an important role in optimising quantum circuit execution by systematically evaluating different configurations of compilation strategies and hardware settings. In this work, we study the impact of layout methods, qubit routing techniques, compiler optimization levels, and hardware-specific properties, including noise characteristics, topological structures, connectivity densities, and device sizes. By traversing these dimensions, we aim to understand how compilation choices interact with hardware features. A central question in our study is whether carefully selected device parameters and mapping strategies, including initial layouts and routing heuristics, can mitigate hardware-induced errors beyond standard error mitigation methods. Our results show that choosing the right software strategies (e.g., layout and routing) and tailoring hardware properties (e.g., reducing noise or leveraging connectivity) significantly enhances the fidelity of quantum circuit executions. We provide performance estimates using metrics such as circuit depth, gate count, and expected fidelity. These findings highlight the value of hardware-software co-design, especially as quantum systems scale and move toward error-corrected computing. Our simulations, though noisy, include quantum error correction (QEC) scenarios, revealing similar sensitivities to layout and connectivity. This suggests that co-design principles will be vital for integrating QEC in future devices. Overall, we offer practical guidance for co-optimizing mapping, routing, and hardware configuration in real-world quantum computing.

Problem

• Exploring compilation and hardware co-design for quantum circuit optimization
• Investigating if device parameters and mapping strategies reduce hardware errors
• Evaluating software strategies and hardware properties to improve circuit fidelity

Innovation

• Hardware-software co-design for quantum optimization
• Systematic evaluation of compilation and hardware settings
• Tailoring device parameters to mitigate hardware errors