ARIANNA: An Automatic Design Flow for Fabric Customization and eFPGA Redaction

2025-06-01

AI Summary

To address the security-overhead trade-off in IP protection within the global IC supply chain, this paper proposes a redaction-oriented co-design methodology for embedded FPGAs (eFPGAs): replacing general-purpose embedded logic with customized programmable fabrics to automatically and securely conceal critical module functionality. We introduce the first co-design flow tailored specifically for redaction objectives and propose two efficient heuristic algorithms that significantly reduce design-space exploration cost under rigorous security guarantees. Our technical approach encompasses bitstream sensitivity analysis, automated redaction-region partitioning, bespoke fabric synthesis and mapping, and quantitative security-strength evaluation. Experimental results demonstrate that, compared to conventional eFPGA-based solutions, our method reduces redaction-related area and power overhead by 3.3×, improves fabric utilization by 4×, and has been validated across multiple industrial-scale benchmark circuits.

Technology Category

• Machine Learning: Hardware-aware ML
• Natural Language Processing: Safety and Robustness
• Computer Vision: Adversarial Attacks & Robustness

Application Category

• Security and Privacy: Large-scale security measurements
• Responsible Web: Measurement, analysis, and circumvention of Web censorship
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems

Abstract

In the modern global Integrated Circuit (IC) supply chain, protecting intellectual property (IP) is a complex challenge, and balancing IP loss risk and added cost for theft countermeasures is hard to achieve. Using embedded configurable logic allows designers to completely hide the functionality of selected design portions from parties that do not have access to the configuration string (bitstream). However, the design space of redacted solutions is huge, with trade-offs between the portions selected for redaction and the configuration of the configurable embedded logic. We propose ARIANNA, a complete flow that aids the designer in all the stages, from selecting the logic to be hidden to tailoring the bespoke fabrics for the configurable logic used to hide it. We present a security evaluation of the considered fabrics and introduce two heuristics for the novel bespoke fabric flow. We evaluate the heuristics against an exhaustive approach. We also evaluate the complete flow using a selection of benchmarks. Results show that using ARIANNA to customize the redaction fabrics yields up to 3.3 × lower overheads and 4 × higher eFPGA fabric utilization than a one-fits-all fabric as proposed in prior works.

Problem

• Protecting IC intellectual property with configurable logic
• Optimizing trade-offs in design redaction and eFPGA configuration
• Reducing overheads and improving fabric utilization in IP security

Innovation

• Automatic flow for fabric customization
• Heuristics for bespoke fabric design
• Security evaluation of redaction fabrics