RulePlanner: All-in-One Reinforcement Learner for Unifying Design Rules in 3D Floorplanning

2026-01-30

AI Summary

This work proposes the first unified deep reinforcement learning framework for 3D integrated circuit placement that effectively handles the complex and diverse design rules prevalent in real-world applications. Existing approaches offer limited support for such rules and often require extensive manual post-processing. The proposed method encodes multiple classes of realistic 3D placement constraints into a matrix representation and integrates them into the learning process through action-space constraints and a reward mechanism quantifying rule compliance. This enables end-to-end generation of rule-compliant placements without human intervention. The framework is designed for flexible incorporation of new rules and demonstrates strong scalability and transferability. Experimental results on public benchmarks show significant reductions in rule violations, minimal need for manual correction, and robust generalization to unseen circuits.

Technology Category

• Planning, Routing, and Scheduling: Learning for Planning and Scheduling
• Constraint Satisfaction and Optimization: Constraint Learning and Acquisition
• Machine Learning: Reinforcement Learning

Application Category

• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

Floorplanning determines the coordinate and shape of each module in Integrated Circuits. With the scaling of technology nodes, in floorplanning stage especially 3D scenarios with multiple stacked layers, it has become increasingly challenging to adhere to complex hardware design rules. Current methods are only capable of handling specific and limited design rules, while violations of other rules require manual and meticulous adjustment. This leads to labor-intensive and time-consuming post-processing for expert engineers. In this paper, we propose an all-in-one deep reinforcement learning-based approach to tackle these challenges, and design novel representations for real-world IC design rules that have not been addressed by previous approaches. Specifically, the processing of various hardware design rules is unified into a single framework with three key components: 1) novel matrix representations to model the design rules, 2) constraints on the action space to filter out invalid actions that cause rule violations, and 3) quantitative analysis of constraint satisfaction as reward signals. Experiments on public benchmarks demonstrate the effectiveness and validity of our approach. Furthermore, transferability is well demonstrated on unseen circuits. Our framework is extensible to accommodate new design rules, thus providing flexibility to address emerging challenges in future chip design. Code will be available at: https://github.com/Thinklab-SJTU/EDA-AI

Problem

• 3D floorplanning
• design rules
• rule violations
• integrated circuits
• post-processing

Innovation

• reinforcement learning
• 3D floorplanning
• design rule unification
• matrix representation
• constraint-aware action space