Problem
Research questions and friction points this paper is trying to address.
on-chip inductors
millimeter-wave integrated circuits
inverse design
layout synthesis
nonlinear geometry-to-performance mapping
HFORD: Hybrid Forward Optimization and Reverse Design Method and Its Applications to On-Chip Millimeter-Wave Inductive Elements
🤖 AI Summary
On-chip millimeter-wave inductor layout synthesis faces significant challenges, including strong geometric–performance nonlinearities, high computational cost of full-wave electromagnetic simulation, topology dependence, and non-uniqueness in inverse design. To address these issues, this work proposes HFORD, a hierarchical synthesis framework that bridges circuit specifications to physical layouts. HFORD employs a unified core to map performance targets into layout seeds and integrates forward optimization with inverse design to accelerate synthesis. It enhances coverage of critical regions via sparse-fitting sampling, reduces modeling dimensionality through compact response coefficients, selects optimal topologies using random forests, generates spectral features with a variational autoencoder, and performs probabilistic inverse mapping via a mixture density network, with particle swarm optimization exploring the latent space. In two design cases, HFORD reduces the design cycle from several hours to just minutes, achieving substantial efficiency gains.
📝 Abstract
On-chip inductive elements are pivotal in determining both the silicon footprint and performance of millimeter-wave (mmWave) integrated circuits. However, the layout-level synthesis of these passive devices is severely challenged by highly nonlinear geometry-to-performance mappings, computationally expensive full-wave electromagnetic simulations, topology-dependent design spaces, and the inherent non-uniqueness of inverse design. To overcome these bottlenecks, we propose a hybrid forward optimization and reverse design (HFORD) method for the target-to-layout synthesis of mmWave inductive elements. Utilizing a unified core to map device-level requirements to layout-level seeds, HFORD structures direct device targets and translates circuit specifications into a hierarchical synthesis flow. Specifically, sparse-fitting sampling is introduced to improve coverage across critical performance regions, while compact response-fitting coefficients significantly reduce training dimensionality. The HFORD core integrates a random forest for topology selection, a variational autoencoder for spectral feature generation, a mixture density network for probabilistic inverse mapping, and particle swarm optimization for latent space exploration. This integration improves the feasibility of the generated layout seeds under design rule check (DRC) constraints. Two design examples demonstrate that the proposed method accelerates the design cycle from hours to minutes compared to conventional optimization methods.
Innovation
Methods, ideas, or system contributions that make the work stand out.
hybrid forward-reverse design
on-chip inductors
machine learning for EM design
inverse design
millimeter-wave ICs
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