DejaVu: Why You Should Write to Your DRAM Rows Twice, Carefully

2026-06-20

AI Summary

This study addresses a critical oversight in conventional DRAM disturbance error testing: the dependence of read disturbance on prior write patterns, which existing methods neglect, leading to biased reliability assessments. The authors empirically identify and name this effect the “DejaVu phenomenon,” demonstrating that repeatedly writing identical data enhances a row’s resilience to disturbance, whereas writing complementary data exacerbates its vulnerability. Through experiments on commercial DDR4 chips, controlled write patterns, and analysis of Processing-in-Memory (PIM) reliability, they reveal that this behavior stems from insufficient charge recovery and trap-state dynamics within DRAM cells. Their findings show that the DejaVu effect improves ACmin on average and reduces failing bitlines by 32.7% in MAJ-3 operations. However, they also show that current mitigation schemes must lower their activation thresholds to remain effective, incurring a 6.3% performance overhead, thereby necessitating updates to both testing protocols and protection mechanisms.

Abstract

We provide the first experimental demonstration of DejaVu, a phenomenon where the data previously written to DRAM cells affects DRAM's vulnerability to read disturbance. Our experimental characterization using 112 COTS DDR4 DRAM chips from all three major manufacturers shows that, compared to the baseline where we initialize the victim row by writing to it only once, 1) overwriting it with the opposite data reduces ACmin, the minimum aggressor row activation count to induce a bitflip, and 2) writing the same data twice increases ACmin. We provide two hypotheses to explain DejaVu. First, we hypothesize that overwriting the victim row with opposite data values causes under-restoration of charge in DRAM cells. Second, we hypothesize that overwriting the victim row changes charge trap states in the active region, affecting read-disturbance-induced cell leakage current. We conduct controlled characterization to provide insight into these hypotheses. We further characterize the reliability of Processing-Using-DRAM (PUD) operations with DRAM rows initialized with DejaVu patterns. Our characterization of 32-row MAJ-3 operation shows that overwriting the DRAM rows used in the operation reduces the number of bitlines that fail to reliably perform MAJ-3 by 32.7% on average compared to the baseline where rows are written only once. Based on our observations, we describe two major implications of DejaVu. We show how DRAM testing and characterization methodologies should account for DejaVu to accurately characterize read disturbance vulnerability under fixed data patterns and rigorously study data-pattern effects without unintended interference from DejaVu. We also evaluate the performance overhead of read disturbance mitigation techniques when thresholds need to be lowered to be secure against DejaVu, showing a 6.3% overhead when reducing the threshold by 20%.

Problem

• DRAM
• read disturbance
• bitflip
• DejaVu
• reliability

Innovation

• DejaVu
• read disturbance
• DRAM reliability
• data pattern effect
• Processing-In-Memory