Row-Based Layout Synthesis for Analog Circuits Using Height-Quantized Primitives

2026-06-19

AI Summary

At advanced technology nodes, the tight coupling between layout and electrical performance in analog circuits poses significant challenges for automated placement. This work proposes a row-height-quantized cell-based layout synthesis methodology, systematically introducing row-height quantization into analog circuit design for the first time. By optimizing row-height structures, modeling layout constraints, and enabling automatic mapping of analog modules onto quantized rows, the approach effectively bridges the performance gap between schematic and post-layout stages. Experimental results across multiple test cases demonstrate that the method achieves performance close to manual custom design, reducing the schematic-to-post-layout performance deviation by up to 68.5% and decreasing area overhead by as much as 24.1%.

Abstract

Restrictive design rules and strong layout-dependent effects have tightened the coupling between physical layout decisions and electrical performance in advanced process nodes, such as FinFET, making analog and mixed-signal (AMS) layout automation increasingly difficult. This paper presents a quantized row-height layout synthesis methodology for AMS circuits, a methodology that has previously been shown to reduce the simulation-to-silicon gap. The proposed flow optimizes a row height fabric from circuit requirements and layout constraints while mapping analog building blocks into quantized-height rows. Results on multiple testcases demonstrate that the proposed flow synthesizes layouts with similar postlayout performance relative to less-constrained custom baseline designs, with comparable performance metrics. Our quantized-height designs are shown to reduce the schematic-to-postlayout performance gap by up to 68.5% and result in lower area for most of our testcases, with a maximum area reduction of 24.1%.

Problem

• analog layout automation
• layout-dependent effects
• restrictive design rules
• FinFET
• schematic-to-postlayout gap

Innovation

• height-quantized primitives
• row-based layout synthesis
• analog layout automation
• layout-dependent effects
• schematic-to-postlayout gap