COMPOSE: Static Timing-driven Composable Reconfigurable Architecture for Accelerating Recurrence-Bound Loops

2026-06-19

AI Summary

Traditional coarse-grained reconfigurable architectures (CGRAs) suffer from limited parallelism, high register pressure, and reduced energy efficiency due to fixed processing elements (PEs) and static scheduling, which struggle to handle inter-iteration dependencies effectively. This work proposes a composable CGRA architecture that dynamically fuses PEs at compile time based on static timing information. By enabling cross-iteration operation scheduling, exploiting timing slack, and deferring the write-back of intermediate results, the approach overcomes the constraints of fixed PEs, alleviates inter-iteration dependencies, and reduces memory traffic. Experimental results demonstrate that the proposed method achieves an average 1.6× performance improvement and a 2.9× reduction in energy-delay product (EDP) across diverse workloads, with negligible area and power overhead.

Abstract

Coarse-Grained Reconfigurable Architectures (CGRAs) provide a spatially programmable substrate well suited for accelerating compute-intensive workloads with abundant parallelism. However, traditional CGRA execution models rely on rigid, fixed-size processing elements (PEs) that are statically bound to individual operations, which forces inter-iteration dependencies to be resolved through serialized scheduling. This limits throughput and reduces parallelism across loop iterations. Moreover, static execution schedules often fail to exploit available timing slack between operations, leading to resource underutilization and increased latency. The frequent registering of intermediate results further exacerbates pressure on register files and local memories, introducing data movement overheads that reduce energy efficiency, particularly in power or memory constrained environments. To address these challenges, we introduce COMPOSE, a composable CGRA architecture that enables dynamic formation of PEs at compile time guided by static timing information. By spatially fusing operations across loop iterations and selectively utilizing slack, COMPOSE resolves inter-iteration dependencies that limit throughput and enables low latency execution by reducing slack wastage. Additionally, the architecture reduces register file pressure by deferring output registration when intermediate values remain locally consumable, which significantly lowers redundant memory traffic. Across a diverse set of workloads, COMPOSE on average delivers 1.6x performance improvement and 2.9x EDP reduction over state-of-the-art (SOTA), at minimal area and power overheads.

Problem

• Coarse-Grained Reconfigurable Architecture
• Recurrence-Bound Loops
• Static Timing
• Inter-Iteration Dependencies
• Register File Pressure

Innovation

• composable CGRA
• static timing-driven
• inter-iteration dependency
• timing slack utilization
• register file pressure reduction