ETM2: Empowering Traditional Memory Bandwidth Regulation using ETM

2026-03-17

AI Summary

This work addresses the challenge of achieving fine-grained, portable, and rapidly responsive memory bandwidth regulation in real-time multicore systems. It proposes the first hardware-assisted memory bandwidth regulator leveraging Arm’s CoreSight Embedded Trace Macrocell (ETM) to enable interrupt-driven, per-core bandwidth control with microsecond-level temporal resolution. The approach incurs minimal software overhead and effectively bridges the gap between MemPol—known for high precision—and MemGuard—valued for its portability—while supporting novel regulation policies. Experimental evaluations across multiple 64-bit Arm platforms, including the Zynq UltraScale+, demonstrate that the proposed solution outperforms existing methods in terms of effectiveness, scalability, and regulation accuracy.

Technology Category

• Machine Learning: Hardware-aware ML
• Multiagent Systems: Mechanism Design
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments
• Security and Privacy: Large-scale security measurements
• Responsible Web: Technology governance, policy, and regulations

Abstract

The Embedded Trace Macrocell (ETM) is a standard component of Arm's CoreSight architecture, present in a wide range of platforms and primarily designed for tracing and debugging. In this work, we demonstrate that it can be repurposed to implement a novel hardware-assisted memory bandwidth regulator, providing a portable and effective solution to mitigate memory interference in real-time multicore systems. ETM2 requires minimal software intervention and bridges the gap between the fine-grained microsecond resolution of MemPol and the portability and reaction time of interrupt-based solutions, such as MemGuard. We assess the effectiveness and portability of our design with an evaluation on a large number of 64-bit Arm boards, and we compare ETM2 with previous works using a setup based on the San Diego Vision Benchmark Suite on the AMD Zynq UltraScale+. Our results show the scalability of the approach and highlight the design trade-offs it enables. ETM2 is effective in enforcing per-core memory bandwidth regulation and unlocks new regulation options that were infeasible under MemGuard and MemPol.

Problem

• memory interference
• memory bandwidth regulation
• real-time multicore systems
• per-core regulation

Innovation

• ETM
• memory bandwidth regulation
• real-time multicore systems
• hardware-assisted control
• CoreSight