HSF-S: Speed-Optimized Compilation and Acceleration for Hybrid Schrodinger-Feynman Quantum Circuit Emulation

2026-07-11

AI Summary

This work addresses the exponential growth in path count during hybrid Schrödinger–Feynman (HSF) quantum circuit simulation, caused by cross-boundary two-qubit gates, which existing GPU- or FPGA-based simulators fail to optimize due to their lack of path-centric design. The paper proposes HSF-S, a framework co-designed with compiler and accelerator components that transforms circuits into an HSF-compatible basis, constructs a path-cost model, and integrates dependency-preserving reordering with a discounted-gain SWAP insertion strategy to drastically suppress cross-boundary interactions while preserving semantic correctness. It presents the first specialized compiler-hardware co-architecture for HSF simulation, featuring a non-regressive selector to prevent path-cost degradation and avoiding full state-vector instantiation. Evaluated on 56 benchmark circuits, HSF-S achieves floating-point precision limits, reduces effective path cost by up to 90.0%, accelerates typical tasks from timeout to sub-second execution, and demonstrates up to 4.34× speedup on a prototype processor.

Abstract

Hybrid Schrodinger-Feynman (HSF) simulation offers an attractive memory-path tradeoff for exact quantum-circuit emulation, but its practical runtime is often dominated by exponential path growth from cross-boundary two-qubit gates. Existing GPU and FPGA quantum simulators are largely optimized for full-state Schrodinger execution and therefore do not align well with HSF's path-centric workflow. This paper presents HSF-S, a compiler-accelerator co-designed framework for exact HSF-based quantum circuit emulation. HSF-S lowers input circuits to an HSF-compatible basis, formulates a rank-aware effective path-cost model, and applies dependency-preserving reordering together with discounted-gain SWAP insertion to suppress recurring cross-boundary interactions while preserving exact circuit semantics. A regression-free selector guarantees that the compiled circuit never increases effective path cost relative to the naive lowered baseline. We further design a dedicated HSF-S accelerator and execution flow, and integrate them into a stand-alone processor for efficient per-path dual-slice evaluation and final accumulation without materializing the full state vector. Across 56 benchmark circuits, HSF-S matches reference amplitudes to within floating-point precision, reduces effective path cost by up to 90.0%, and substantially improves practical tractability, including representative timeout-to-sub-second reductions under a 1-hour budget. On the resulting compiled workloads, the HSF-S processor prototype delivers up to 4.34x additional speedup.

Problem

• Hybrid Schrodinger-Feynman
• quantum circuit emulation
• cross-boundary two-qubit gates
• path explosion
• exact simulation

Innovation

• Hybrid Schrodinger-Feynman
• quantum circuit compilation
• path-cost optimization
• SWAP insertion
• dedicated accelerator