Arisca: A Parameterized Symbolic Algebra Framework for Arithmetic Circuit Verification

2026-07-11

AI Summary

This work addresses the scalability bottlenecks in formal verification of gate-level highly optimized arithmetic circuits, which stem from state-space explosion and intermediate polynomial blowup. To overcome these challenges, the paper proposes a parameterized symbolic algebraic verification framework that uniformly models general arithmetic circuits—supporting arbitrary combinations of addition and multiplication—as multivariate polynomials. The approach integrates existing techniques through a parameterized algebraic reduction theory, with key innovations including a unified parameter space encompassing multiple state-of-the-art methods, along with novel algorithms for HA-preserving extraction, density-aware elimination detection, and conservative polynomial size estimation. Experimental results on standard multipliers and practical arithmetic units such as multiply-adders and dot-product engines demonstrate that the proposed method achieves state-of-the-art verification performance.

Abstract

Formal verification of highly optimized arithmetic circuits at the gate-level remains a significant challenge due to the state space explosion problem. Although Symbolic Computer Algebra (SCA) offers a scalable theoretical foundation by modeling circuits as multivariate polynomials, practical implementations frequently suffer from the explosion of the size of intermediate polynomials. State-of-the-art SCA tools typically rely on fixed heuristics and restrict their application to standard multipliers. A fixed heuristic is insufficient for structurally diverse arithmetic circuits, as it often fails to generalize across all cases. In this paper, we introduce Arisca, an open-source parameterized verification framework for \textbf{Ari}thmetic circuits using \textbf{S}ymbolic \textbf{C}omputer \textbf{A}lgebra. Arisca establishes a generalized parameter space that unifies previously isolated state-of-the-art (SOTA) techniques as specific configurations within a broader algebraic reduction theory. To fundamentally transplant and elevate previous methods, we propose several algorithmic improvements, such as an HA-preserving extraction strategy, density-based vanishing detection, and conservative polynomial size estimation. In addition, Arisca expands the verification scope to encompass general arithmetic circuits with any combination of addition and multiplication, such as multiply-accumulators and dot-product units. Extensive evaluations demonstrate that Arisca achieves SOTA performance in a comprehensive suite of multiplier benchmarks and a diverse array of practical arithmetic cases.

Problem

• arithmetic circuit verification
• symbolic computer algebra
• state space explosion
• polynomial blowup
• formal verification

Innovation

• Symbolic Computer Algebra
• Arithmetic Circuit Verification
• Parameterized Framework
• Polynomial Size Explosion
• Algebraic Reduction