Automatic Verification of Floating-Point Accumulation Networks

2025-05-24

AI Summary

Floating-point accumulation networks (FPANs) are critical components in compensated summation and double-precision floating-point algorithms; however, their error analysis is notoriously complex, and existing approaches often lack rigorous formal verification—some published error bounds have even been refuted. Method: We propose the first fully automated, machine-verifiable framework for FPAN correctness verification. It introduces a novel floating-point abstraction model that precisely captures leading/trailing zero/one patterns in sign, exponent, and significand; integrates SMT solving with formal verification to automatically synthesize error bounds tight to 1 bit; and designs a new double-precision-addition FPAN. Contribution/Results: Our framework guarantees formal correctness while achieving both higher accuracy and faster execution than state-of-the-art baselines. Experiments successfully generate machine-checked proofs for multiple classic FPANs, with error bounds provably tight at the bit level.

Technology Category

• Machine Learning: Calibration & Uncertainty Quantification
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization

Abstract

Floating-point accumulation networks (FPANs) are key building blocks used in many floating-point algorithms, including compensated summation and double-double arithmetic. FPANs are notoriously difficult to analyze, and algorithms using FPANs are often published without rigorous correctness proofs. In fact, on at least one occasion, a published error bound for a widely used FPAN was later found to be incorrect. In this paper, we present an automatic procedure that produces computer-verified proofs of several FPAN correctness properties, including error bounds that are tight to the nearest bit. Our approach is underpinned by a novel floating-point abstraction that models the sign, exponent, and number of leading and trailing zeros and ones in the mantissa of each number flowing through an FPAN. We also present a new FPAN for double-double addition that is faster and more accurate than the previous best known algorithm.

Problem

• Automatic verification of floating-point accumulation networks (FPANs)
• Producing computer-verified proofs for FPAN correctness properties
• Developing a faster and more accurate double-double addition FPAN

Innovation

• Automatic procedure for FPAN verification
• Novel floating-point abstraction model
• Faster and more accurate double-double addition