Enable Lightweight and Precision-Scalable Posit/IEEE-754 Arithmetic in RISC-V Cores for Transprecision Computing

2025-05-25

AI Summary

To address the demand for lightweight, precision-scalable floating-point arithmetic in RISC-V processors, this paper proposes a unified hardware architecture enabling deep integration of posit and IEEE-754 floating-point computation—first of its kind. Methodologically, we design a lightweight posit encode/decode unit supporting dynamic exponent-width configuration for multiple precisions (e.g., p = 8–32), reuse and extend existing RISC-V FPU hardware, and define custom ISA instructions (evolving from RV32/64F/D) fully compatible with IEEE-754. Our contributions are threefold: (1) the first software–hardware co-designed unified floating-point unit; (2) 47.9% reduction in LUTs and 57.4% reduction in FFs versus state-of-the-art designs; and (3) 2.54× throughput improvement in GEMM kernels, significantly enhancing energy efficiency across mixed-precision computations.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Biometrics, Face, Gesture & Pose
• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving

Application Category

• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Responsible Web: Data and user privacy-enhancing technologies for the Web
• User Modeling, Personalization and Recommendation: Fairness-aware retrieval and ranking

Abstract

While posit format offers superior dynamic range and accuracy for transprecision computing, its adoption in RISC-V processors is hindered by the lack of a unified solution for lightweight, precision-scalable, and IEEE-754 arithmetic compatible hardware implementation. To address these challenges, we enhance RISC-V processors by 1) integrating dedicated posit codecs into the original FPU for lightweight implementation, 2) incorporating multi/mixed-precision support with dynamic exponent size for precision-scalability, and 3) reusing and customizing ISA extensions for IEEE-754 compatible posit operations. Our comprehensive evaluation spans the modified FPU, RISC-V core, and SoC levels. It demonstrates that our implementation achieves 47.9% LUTs and 57.4% FFs reduction compared to state-of-the-art posit-enabled RISC-V processors, while achieving up to 2.54$ imes$ throughput improvement in various GEMM kernels.

Problem

• Lack of unified lightweight posit arithmetic in RISC-V
• Need for precision-scalable posit/IEEE-754 compatible hardware
• High resource overhead in existing posit-enabled RISC-V designs

Innovation

• Integrating posit codecs into FPU for lightweight design
• Supporting multi/mixed-precision with dynamic exponent size
• Customizing ISA extensions for IEEE-754 compatibility