Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation

2025-05-26

AI Summary

In 3D heterogeneous integration and chiplet-based systems, poor controllability/observability of deep-logic-level nodes degrades traditional scan-based DFT test quality. To address this, we propose LITE, an ATPG-aware lightweight scan enhancement methodology. LITE introduces a novel hardware-free ATPG-aware scan instrumentation architecture that leverages circuit-level scan chain restructuring, ATPG-guided automated insertion, and functional flip-flop timing-compatibility modeling—enabling low-cost, scalable control and observation of multiple internal nodes by reusing existing functional flip-flops. Experimental results demonstrate that LITE significantly improves ATPG pattern generation efficiency and random-pattern test coverage, while reducing hardware overhead by over 50% compared to conventional test-point insertion. LITE thus achieves superior test quality with minimal design cost, offering a practical solution for complex 3D and chiplet systems.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Sampling/Simulation-based Search
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories

Application Category

• Security and Privacy: Large-scale security measurements
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization

Abstract

Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D heterogeneous integration and chiplet-based systems, the role of scan is becoming ever more important due to its ability to make internal design nodes controllable and observable in a systematic and scalable manner. However, the effectiveness of scan-based DFT suffers from poor testability of internal nodes for complex circuits at deep logic levels. Existing solutions to address this problem primarily rely on Test Point Insertion (TPI) in the nodes with poor controllability or observability. However, TPI-based solutions, while an integral part of commercial practice, come at a high design and hardware cost. To address this issue, in this paper, we present LITE, a novel ATPG-aware lightweight scan instrumentation approach that utilizes the functional flip-flops in a scan chain to make multiple internal nodes observable and controllable in a low-cost, scalable manner. We provide both circuit-level design as well as an algorithmic approach for automating the insertion of LITE for design modifications. We show that LITE significantly improves the testability in terms of the number of patterns and test coverage for ATPG and random pattern testability, respectively, while incurring considerably lower overhead than TPI-based solutions.

Problem

• Improving testability of deep logic nodes in scan-based DFT
• Reducing hardware cost of Test Point Insertion (TPI) solutions
• Enhancing ATPG and random pattern test coverage efficiency

Innovation

• ATPG-aware lightweight scan instrumentation approach
• Utilizes functional flip-flops in scan chain
• Low-cost, scalable testability improvement