Simulation-Guided Approximate Logic Synthesis Under the Maximum Error Constraint

2025-05-22

AI Summary

This work addresses Approximate Logic Synthesis (ALS) under a user-specified maximum error constraint, aiming to generate area-, delay-, and power-optimized approximate circuits while strictly guaranteeing worst-case error bounds. We propose a simulation-guided automated synthesis framework featuring two key innovations: (i) the first simulation-driven LAC (Logic Approximation Cell) pruning and SAT-based selection acceleration mechanism, and (ii) an iterative constraint-satisfaction LAC filtering strategy, enabling scalable ALS on ultra-large EPFL benchmarks (up to 38,540 nodes)—a previously unsolved challenge. Compared to state-of-the-art methods, our approach achieves a 30.6× speedup, reduces area by 18.2%, lowers delay by 4.9%, and—critically—is the first to enable efficient ALS of kilo-scale circuits under strict maximum-error constraints.

Technology Category

• Search and Optimization: Sampling/Simulation-based Search
• Constraint Satisfaction and Optimization: Satisfiability
• Machine Learning: Hardware-aware ML

Application Category

• Graph Algorithms and Modeling for the Web: Algorithms and analysis for incomplete, noisy, or partially observed Web-related graphs
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications

Abstract

Approximate computing is an effective computing paradigm for improving energy efficiency of error-tolerant applications. Approximate logic synthesis (ALS) is an automatic process to generate approximate circuits with reduced area, delay, and power, while satisfying user-specified error constraints. This paper focuses on ALS under the maximum error constraint. As an essential error metric that provides a worst-case error guarantee, the maximum error is crucial for many applications such as image processing and machine learning. This work proposes an efficient simulation-guided ALS flow that handles this constraint. It utilizes logic simulation to 1) prune local approximate changes (LACs) with large errors that violate the error constraint, and 2) accelerate the SAT-based LAC selection process. Furthermore, to enhance scalability, our ALS flow iteratively selects a set of promising LACs satisfying the error constraint to improve the efficiency. The experimental results show that compared with the state-of-the-art method, our ALS flow accelerates by 30.6 times, and further reduces circuit area and delay by 18.2% and 4.9%, respectively. Notably, our flow scales to large EPFL benchmarks with up to 38540 nodes, which cannot be handled by any existing ALS method for maximum error.

Problem

• ALS under maximum error constraint for energy efficiency
• Simulation-guided pruning of high-error local changes
• Scalable LAC selection for large circuit benchmarks

Innovation

• Simulation-guided pruning of high-error local changes
• SAT-based accelerated selection of approximate changes
• Iterative scalable selection for large circuit benchmarks