Controllable Quantum Memory Capacity in Quantum Reservoir Networks with Tunable partial-SWAPs

2026-05-12

AI Summary

This work addresses the limited understanding and poor controllability of memory capacity in existing quantum reservoir computing architectures, which, despite exhibiting decaying memory, lack explicit mechanisms for tuning memory dissipation. To overcome this, the authors propose a novel dual-register architecture based on tunable partial SWAP operations, enabling the first explicit control over the memory decay rate in quantum reservoirs. The proposed mechanism is efficiently implementable on gate-based quantum processors and is theoretically grounded in controlled amplitude damping channels. Its efficacy is validated through simulations and experiments on IBM quantum hardware using both randomized short-term memory capacity (STMC) and the NARMA-5 benchmark task. Results demonstrate that the approach significantly enhances the tunability of memory capacity and substantially improves model performance on near-term noisy intermediate-scale quantum (NISQ) devices.

Abstract

In the field of quantum reservoir computing (QRC), many different computational models and architectures have been proposed. From these models, we identify feedback based models -- which use a feedback mechanism to re-embed classical measurements from the QRC -- and recurrent models -- which use a multi-register approach with memory and readout qubits -- as the two major competing architectures that have been discussed and validated on hardware. In this paper, we advance upon the recurrent architectures, which employ a two register approach to endow the QRC with a fading memory. While these approaches have been validated on hardware and have demonstrated great real-world performance on noisy-intermediate-scale-quantum (NISQ) quantum processing units (QPUs), the exact mechanism through which the memory capacity arises is not completely understood or fully controllable. With this, we augment the recurrent approaches and present a hardware-realizable mechanism, which we call a tunable partial-SWAP, that allows for the direct control of the rate of memory dissipation from a QRN implemented on a gate-based QPU. The theory behind this mechanism is discussed in terms of a controlled amplitude-damping channel and validation experiments using a randomized short-term memory capacity (STMC) recall benchmark and the NARMA-5 dataset are conducted using simulation and IBM QPUs, respectively.

Problem

• quantum reservoir computing
• memory capacity
• recurrent architectures
• memory dissipation
• NISQ

Innovation

• tunable partial-SWAP
• quantum reservoir computing
• memory capacity control
• amplitude-damping channel
• NISQ