Trojan-Resilient NTT: Protecting Against Control Flow and Timing Faults on Reconfigurable Platforms

2026-01-30

AI Summary

This work addresses the security threat posed by hardware Trojans that compromise lattice-based cryptographic implementations by tampering with control signals to disrupt the Number Theoretic Transform (NTT) control flow or induce anomalous timing behavior. To counter this, the paper proposes a highly robust NTT architecture that, for the first time, integrates joint detection of control-flow and timing faults with an adaptive error-correction mechanism directly into the NTT hardware implementation. The design further incorporates countermeasures against soft analytical side-channel attacks (SASCA). Experimental results on an Artix-7 FPGA demonstrate that the proposed architecture efficiently detects and corrects a wide range of hardware Trojan-induced faults, achieving high-protection success rates for lattice-based schemes such as Kyber, with only modest overhead in area and timing.

Technology Category

• Machine Learning: Hardware-aware ML
• Natural Language Processing: Safety and Robustness
• Computer Vision: Adversarial Attacks & Robustness

Application Category

• Security and Privacy: Applications of cryptography
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems
• Responsible Web: Measurement, analysis, and circumvention of Web censorship

Abstract

Number Theoretic Transform (NTT) is the most essential component for polynomial multiplications used in lattice-based Post-Quantum Cryptography (PQC) algorithms such as Kyber, Dilithium, NTRU etc. However, side-channel attacks (SCA) and hardware vulnerabilities in the form of hardware Trojans may alter control signals to disrupt the circuit's control flow and introduce unconventional delays in the critical hardware of PQC. Hardware Trojans, especially on control signals, are more low cost and impactful than data signals because a single corrupted control signal can disrupt or bypass entire computation sequences, whereas data faults usually cause only localized errors. On the other hand, adversaries can perform Soft Analytical Side Channel Attacks (SASCA) on the design using the inserted hardware Trojan. In this paper, we present a secure NTT architecture capable of detecting unconventional delays, control-flow disruptions, and SASCA, while providing an adaptive fault-correction methodology for their mitigation. Extensive simulations and implementations of our Secure NTT on Artix-7 FPGA with different Kyber variants show that our fault detection and correction modules can efficiently detect and correct faults whether caused unintentionally or intentionally by hardware Trojans with a high success rate, while introducing only modest area and time overheads.

Problem

• Hardware Trojans
• Control Flow Faults
• Timing Faults
• Side-Channel Attacks
• Number Theoretic Transform

Innovation

• Trojan-resilient NTT
• control-flow protection
• timing fault detection
• SASCA mitigation
• adaptive fault correction