🤖 AI Summary
This work addresses the critical performance bottleneck in zero-knowledge proof systems caused by front-end trace generation in zero-knowledge virtual machines (zkVMs). It presents the first heterogeneous hardware acceleration architecture tailored specifically for zkVM front-end execution, featuring coordinated processing units for main and parallel permutation traces alongside a lightweight instruction set extension to enable fine-grained hardware-software co-design. Unlike prior efforts that focus exclusively on back-end proving, this architecture targets the underexplored front-end phase. ASIC implementation results demonstrate a 1,829× speedup in trace generation over a high-performance multicore CPU; when integrated with existing back-end accelerators, the end-to-end proof generation achieves a 963× performance improvement.
📝 Abstract
Zero-knowledge virtual machines (zkVMs) are a key technology for driving the large-scale adoption of zero-knowledge proofs (ZKP), but their performance bottlenecks severely limit their practicality. While current hardware acceleration research has exclusively focused on backend proving, we identify that the frontend execution and trace generation phase is rapidly emerging as the new system bottleneck. To address this challenge, we propose ZK-Tracer, the first hardware accelerator architecture specifically designed for the zkVM frontend. ZK-Tracer features a novel heterogeneous design comprising a Main Trace Unit and parallel Permutation Trace Units. It exposes a fine-grained interface to the host software through a lightweight instruction set extension, enabling efficient task offloading. Our ASIC implementation results demonstrate that ZK-Tracer achieves up to 1829x speedup in trace generation over a high-performance multi-core CPU. When integrated with existing backend proving accelerators, it delivers a remarkable 963x end-to-end performance improvement for the entire ZKP system.