An Energy-Efficient Approximate Posit Multiply-Divide Unit

2026-05-23

AI Summary

This work addresses the high latency, power consumption, and area overhead of conventional division hardware, particularly the lack of efficient approximate implementations in the posit number system. The authors propose a low-precision approximate multiply-divide unit tailored for posits, which uniquely integrates reciprocal approximation directly into the posit decoder. By exploiting the mathematical symmetry inherent in the posit representation, the design rapidly generates reciprocal approximations using a small lookup table (LUT) and a single subtraction operation, while unifying support for both multiplication and division. Implemented in TSMC 90 nm CMOS technology, the proposed unit achieves a 78.8% reduction in power-delay product and occupies only 46.33% of the area compared to an exact division implementation, simultaneously enhancing overall multiplication efficiency within posit-based systems.

Abstract

In modern computing units, division operations are generally slower than other arithmetic operations and require more resources, such as area and power, than multiplication. To reduce the delay, fast division algorithms use an initial approximation of the reciprocal of the divisor and iteratively approach the correct value, followed by multiplication with the dividend. The hardware architecture and choice of algorithm can significantly alter the overall performance of the division unit. This paper proposes a reduced-accuracy division method for the posit number system, which is an alternative to the traditional floating-point system. The proposed design uses a Look-Up Table (LUT) and a single subtraction operation to perform approximate divisor reciprocation by leveragingthemathematicalsymmetriesofthepositnumbersystem.The paper also presents a hardware architecture that combines multiplication and division units. The reciprocal calculation has been incorporated into the posit Decoder, a common unit required to perform any hardware operation with posits. Compared to existing hardware implementations of division, the proposed method requires significantly fewer operations at the cost of perfect rounding for division. The proposed architecture was simulated using the Cadence RTL v7.1 E2 compiler at the TSMC 90 nm process node and achieves a Power Delay Product (PDP) reduction of 78.8% compared to an existing design that performs exact division, while only 46.33% of the area is required. The experimental results also demonstrate the effectiveness of the proposed system in improving the efficiency of multiplication in posit-based systems.

Problem

• division
• posit number system
• energy efficiency
• approximate computing
• hardware architecture

Innovation

• posit number system
• approximate division
• Look-Up Table (LUT)
• Power Delay Product (PDP)
• multiply-divide unit