Implementation and Performance Evaluation of CMOS-integrated Memristor-driven Flip-flop Circuits

2026-02-14

AI Summary

This work proposes a novel sequential logic design methodology that integrates Y₂O₃-based memristors with 90 nm CMOS technology to overcome the limitations of conventional CMOS circuits in area, power consumption, and delay. The approach enables the construction and optimization of various combinational logic gates as well as D, T, JK, and SR flip-flops. Leveraging a validated memristor model within the Cadence Virtuoso platform and SPECTRE simulations, the proposed memristor-driven flip-flop architecture significantly reduces both inter-device and cycle-to-cycle variability. Compared to state-of-the-art alternatives, the resulting circuits achieve approximately 24% reduction in area, 60% lower power consumption, and 58% improvement in delay, thereby delivering a synergistic breakthrough in energy efficiency, compact layout, and high-speed operation.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Mixed Discrete/Continuous Search
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding

Application Category

• Security and Privacy: Large-scale security measurements
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments

Abstract

In this work, we report implementation and performance evaluation of memristor-driven fundamental logic gates, including NOT, AND, NAND, OR, NOR, and XOR, and novel and optimized design of the sequential logic circuits, such as D flip-flop, T-flip-flop, JK-flip-flop, and SR-flip-flop. The design, implementation, and optimization of these logic circuits were performed in SPECTRE in Cadence Virtuoso and integrated with 90 nm CMOS technology node. Additionally, we discuss an optimized design of memristor-driven logic gates and sequential logic circuits, and draw a comparative analysis with the other reported state-of-the-art work on sequential circuits. Moreover, the utilized memristor framework was experimentally pre-validated with the experimental data of Y2O3-based memristive devices, which shows significantly low values of variability during switching in both device-to-device (D2D) and cycle-to-cycle (C2C) operation. The performance metrics were calculated in terms of area, power, and delay of these sequential circuits and were found to be reduced by more than ~24%, 60%, and 58%, respectively, as compared to the other state-of-the-art work on sequential circuits. Therefore, the implemented memristor-based design significantly improves the performance of various logic designs, which makes it more area and power-efficient and shows the potential of memristor in designing various low-power, low-cost, ultrafast, and compact circuits.

Problem

• memristor
• flip-flop
• CMOS integration
• sequential logic circuits
• low-power design

Innovation

• memristor-driven logic
• CMOS integration
• sequential circuits
• low-power design
• performance optimization