Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorer

2025-05-20

AI Summary

Binary and ternary neural network (BNN/TNN) inference on RRAM-based compute-in-memory (CIM) architectures is hindered by device non-idealities, while existing toolchains are fragmented—supporting only compilation, simulation, or design-space exploration (DSE) in isolation—and rely on 8-bit quantization, limiting accuracy and efficiency. Method: This work introduces the first modular CIM toolbox enabling joint DSE for BNNs and TNNs. It integrates RRAM physics-aware modeling, sparsity-aware block-transpose mapping, a customized compiler stack, and an accuracy–hardware co-simulator to unify weight mapping, array mapping, and accuracy evaluation in an end-to-end optimized flow. Contribution/Results: The toolbox overcomes siloed optimization by enabling rapid, cross-parameter accuracy estimation—spanning array sizes, cell variation rates, and mapping strategies—thereby accelerating the full pipeline from early-stage evaluation to chip deployment. Open-source implementation is provided.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories

Application Category

• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• User Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications

Abstract

Using Resistive Random Access Memory (RRAM) crossbars in Computing-in-Memory (CIM) architectures offers a promising solution to overcome the von Neumann bottleneck. Due to non-idealities like cell variability, RRAM crossbars are often operated in binary mode, utilizing only two states: Low Resistive State (LRS) and High Resistive State (HRS). Binary Neural Networks (BNNs) and Ternary Neural Networks (TNNs) are well-suited for this hardware due to their efficient mapping. Existing software projects for RRAM-based CIM typically focus on only one aspect: compilation, simulation, or Design Space Exploration (DSE). Moreover, they often rely on classical 8 bit quantization. To address these limitations, we introduce CIM-Explorer, a modular toolkit for optimizing BNN and TNN inference on RRAM crossbars. CIM-Explorer includes an end-to-end compiler stack, multiple mapping options, and simulators, enabling a DSE flow for accuracy estimation across different crossbar parameters and mappings. CIM-Explorer can accompany the entire design process, from early accuracy estimation for specific crossbar parameters, to selecting an appropriate mapping, and compiling BNNs and TNNs for a finalized crossbar chip. In DSE case studies, we demonstrate the expected accuracy for various mappings and crossbar parameters. CIM-Explorer can be found on GitHub.

Problem

• Optimizing BNN and TNN inference on RRAM crossbars
• Addressing non-idealities in RRAM crossbar operation
• Providing end-to-end design exploration for CIM architectures

Innovation

• Modular toolkit for BNN and TNN optimization
• End-to-end compiler stack with simulators
• Design Space Exploration for RRAM crossbars