Building Reliable Arithmetic Multipliers Under NBTI Aging and Process Variations

2026-05-18

AI Summary

This work addresses the critical reliability challenges posed by hardware aging—particularly Negative Bias Temperature Instability (NBTI)—and process variations in multipliers deployed in CPUs, GPUs, and AI accelerators. It proposes a lightweight NBTI aging mitigation strategy that exploits the sign-invariance property of multiplication to selectively apply two’s-complement transformations, thereby redistributing transistor stress without requiring redundancy or error correction. The approach seamlessly integrates into AI accelerator architectures such as systolic arrays. Circuit-level simulations demonstrate that the technique significantly extends multiplier lifetime with negligible area and delay overhead, making it well-suited for high-throughput AI computing scenarios.

Abstract

Hardware aging poses a significant challenge for integrated circuits (ICs), leading to performance degradation and eventual failure. In this work, we focus on the aging of arithmetic multipliers, which are a cornerstone of modern computing systems including in CPUs, GPUs, and FPGAs, as well as AI accelerators like systolic arrays. In particular, AI workloads, which rely predominantly on multiplications, can accelerate Negative Bias Temperature Instability (NBTI) effects in multipliers. This paper presents a novel aging mitigation technique that leverages the signinvariance property of multiplication. By selectively applying 2s complement transformations to inputs, the method redistributes stress across transistors, reducing the effects of NBTI aging. The proposed method is also integrated into systolic arrays, a common AI accelerator, to demonstrate its efficiency in a high-throughput AI accelerator. Experimental evaluations using Cadence tools show better lifetime compared to natural aging (with no mitigation) baseline, while introducing negligible area and delay overheads.

Problem

• NBTI aging
• arithmetic multipliers
• reliability
• process variations
• hardware aging

Innovation

• NBTI aging mitigation
• sign-invariance
• 2s complement transformation
• systolic array
• arithmetic multiplier reliability