Spiker-LL: An Energy-Efficient FPGA Accelerator Enabling Adaptive Local Learning in Spiking Neural Networks

2026-05-18

AI Summary

This work addresses the challenges of high computational overhead and energy consumption in deploying adaptive, online-learning spiking neural networks (SNNs) on edge devices, where on-chip learning is particularly difficult to implement efficiently. By adopting a hardware-algorithm co-design approach, the authors extend the open-source Spiker+ inference architecture with an STDP-inspired synaptic trace-based local learning rule (STSF) and enhance the FPGA microarchitecture to enable low-overhead, scalable online learning without relying on DSP resources. The resulting accelerator achieves up to 93% accuracy across MNIST, Fashion-MNIST, and DIGITS datasets, with per-inference energy consumption below 0.1 mJ and latency under 1 millisecond—demonstrating, for the first time on a DSP-free FPGA, a compelling combination of high energy efficiency, real-time performance, and online learning capability for SNNs.

Abstract

Deploying adaptive intelligence at the edge remains challenging due to the high computational and energy cost of training neural models. Spiking Neural Networks (SNNs) offer a promising alternative, but enabling on-device learning requires hardware-algorithm co-design. This paper presents SPIKER-LL, an FPGA-based SNN accelerator that extends the open-source Spiker+ inference architecture with efficient support for the STSF local learning rule. Through targeted microarchitectural extensions, SPIKER-LL performs inference and online learning with minimal overhead. Across MNIST, F-MNIST, and DIGITS, it achieves up to 93% accuracy, sub-millisecond latency, and less than 0.1 mJ per inference, while remaining DSP-free and highly scalable for edge-FPGA deployments.

Problem

• edge learning
• Spiking Neural Networks
• on-device learning
• energy efficiency
• adaptive intelligence

Innovation

• Spiking Neural Networks
• FPGA accelerator
• local learning
• energy-efficient
• hardware-algorithm co-design