🤖 AI Summary
This work addresses the significant challenge of inefficient hardware bug localization in large-scale processor designs. The authors propose BluesFL, a novel framework featuring the first block-level, instruction-guided slicing algorithm—Blues—that integrates dataflow analysis, code chunking, and instruction-level program slicing to direct large language models toward critical contextual information while emulating human-like debugging reasoning. Evaluated on a 19K-line SystemVerilog implementation of a RISC-V core, the approach correctly localizes 24 bugs at Top-1 accuracy, achieving a 242.9% improvement over the current state-of-the-art method, with a per-bug localization cost of merely $0.257. This represents a substantial breakthrough in overcoming fault localization bottlenecks in complex processor design.
📝 Abstract
Fault localization in modern processor design code is a critical yet time-consuming step during processor verification. While recent advances in LLM-based techniques for module-level hardware design have shown promising results, automatically localizing bugs in large-scale, project-level processor designs remains challenging. In this paper, we present BluesFL, a novel block-level LLM-based fault localization framework for processor designs. Inspired by the way engineers debug processors, we first propose a dataflow-based code blockization approach to guide LLMs to focus on critical local code context. We further propose a Block-Level Instruction-Oriented Slicing (Blues) algorithm that enables LLMs to mimic human reasoning by analyzing instruction execution paths and processor states. We evaluate BluesFL on a real-world RISC-V processor core comprising 19K lines of SystemVerilog code. Experimental results demonstrate that BluesFL correctly localizes 24 bugs at Top-1, achieving 242.9% improvement over the existing state-of-the-art (7 bugs). Cost analysis shows that BluesFL requires an average of only $0.257 to localize a single bug.