🤖 AI Summary
This work addresses the inefficiencies of traditional early-stage power delivery network (PDN) design, which relies on static or worst-case power assumptions and often leads to over-provisioning of resources and suboptimal routing. The authors propose a workload-aware PDN optimization methodology that, for the first time at the architectural level, incorporates real application-driven dynamic power traces. By performing fine-grained temporal power simulations, the approach generates spatiotemporal power density maps and translates them into current demand profiles to guide tile-level PDN topology planning. This enables adaptive resource allocation aligned with actual application behavior, achieving up to a 32.94% reduction in PDN metal area compared to conventional designs while satisfying IR drop and electromigration constraints.
📝 Abstract
Power Delivery Networks (PDNs) are critical for maintaining voltage integrity in modern multiprocessor systems. Conventional early-stage PDN planning relies on static or worst-case power assumptions, often leading to over-provisioned designs and inefficient use of routing resources. This paper proposes a workload-aware methodology for early-stage PDN optimization based on architectural power traces. Using architectural simulations, temporal power activity is captured at fine granularity and mapped to spatial power density distributions across the chip. These distributions are then translated into current demand profiles to guide PDN topology planning at tile granularity. By incorporating realistic workload behavior, the proposed approach enables adaptive PDN resource allocation during early design stages. Experimental results demonstrate that the method achieves up to 32.94% reduction in PDN metal area compared to conventional worst-case designs, while maintaining compliance with IR drop and electromigration constraints.