Self-Organising Digital Circuits

2026-05-07

AI Summary

This study addresses the lack of biologically inspired adaptive reconfiguration in conventional fault-tolerant computing by proposing a self-organizing digital circuit architecture. Modeling circuit generation and maintenance as a graph meta-learning problem, this work extends the neural cellular automata paradigm by employing topology-masked Transformers to configure Boolean gate look-up tables, thereby enabling circuit self-assembly and dynamic fault rerouting within degraded search spaces. Experimental results demonstrate that the proposed architecture achieves a soft error recovery rate exceeding 99.99% while exhibiting robust cross-scale generalization. By successfully translating biological self-organization principles into digital hardware resilience, this research establishes a novel paradigm for high-reliability computing systems.

Abstract

Fault tolerance in classical computing has traditionally relied on static strategies like hardware redundancy and error-correcting codes. Biological systems, in contrast, exhibit adaptive plasticity, maintaining function through dynamic re-organisation around damage. Inspired by this principle, we introduce Self-Organising Digital Circuits, framing functional logic generation and maintenance as a meta-learning problem on graphs. Our architecture employs a topology-masked Transformer that configures the Lookup Tables (LUT) of a circuit's Boolean gates. Extending the pattern-generation paradigm of Neural Cellular Automata (NCA), it navigates the degenerate Boolean search space to satisfy a computational task, rather than regenerating a fixed target state. We demonstrate that it can self-assemble functional circuits from scratch and rapidly re-route logic around permanent, previously unseen hardware faults. For soft errors, the policy achieves near-perfect recovery (>99.99\% accuracy) from damage sizes far exceeding training conditions. We further observe generalisation across circuit scales: accuracy improves on graphs substantially wider than those seen during training. This work bridges the principles of biological self-organisation with the practical domain of digital hardware.

Problem

• Fault tolerance
• Self-organising digital circuits
• Adaptive plasticity
• Hardware faults
• Dynamic re-organisation

Innovation

• Self-Organising Digital Circuits
• Topology-masked Transformer
• Neural Cellular Automata
• Meta-learning on Graphs
• Fault Tolerance