LLM Assisted Verification Assertion Generation: Challenges and Future Directions

2026-07-08

AI Summary

This work addresses the labor-intensive and error-prone process of manually crafting SystemVerilog Assertions (SVA) from specification documents in assertion-based verification (ABV). It presents the first systematic analysis of the key challenges involved in leveraging large language models (LLMs) for automated SVA generation and proposes a principled methodology that ensures high-quality, standardized outputs. By integrating natural language processing with formal verification techniques, the study formulates guiding principles and practical strategies tailored to the generation of reliable and precise assertions. This approach provides both theoretical grounding and a viable pathway toward building efficient, robust automated verification workflows.

Abstract

Assertion-based Verification (ABV) plays a critical role in the Design Verification (DV) process. However, ABV requires substantial manual effort in generating assertion from specification by verification engineers, making it a time-consuming stage in the chip design flow. With the recent development of Large Language Models (LLMs), researchers have started exploring their use as an assistance in the ABV process, particularly for generating SystemVerilog Assertions (SVAs) from design specification. In this paper, we provide an overview of recent works, highlighting the different methods used to generate SVAs. In particular, we investigate LLM-based SVA generation and ask a central question: How can LLM-based assertion generation be made systematic and quality-aware? While addressing this key question, we provide Key Takeaways at the end of each challenge, summarizing the important methodological insights, and also provide guidelines and directions in solving those challenges that can help generate a high-quality set of assertions using LLMs.

Problem

• Assertion-based Verification
• Large Language Models
• SystemVerilog Assertions
• Design Verification
• Assertion Generation

Innovation

• Large Language Models
• Assertion-based Verification
• SystemVerilog Assertions
• Verification Automation
• Quality-aware Generation