Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking

2026-07-08

AI Summary

This work addresses the significant performance degradation of SAT solvers in logic equivalence checking (LEC) caused by structural perturbations introduced during synthesis and XOR-dense circuit regions. To mitigate this, the authors propose a miter-oriented LUT mapping framework that co-optimizes solver efficiency at the modeling stage. The approach integrates structural alignment, Gaussian elimination–guided algebraic simplification of XOR structures, and a solver-aware LUT selection strategy within a unified paradigm based on LUT-based miters that preserve structural correspondence. This framework explicitly captures high-level logical relationships while guaranteeing equivalence-preserving mappings. Experimental results demonstrate up to a 92.1% reduction in runtime on mainstream SAT solvers, substantially enhancing LEC efficiency.

Abstract

Logic Equivalence Checking (LEC), a fundamental hardware verification task, is often bottlenecked by synthesis-induced structural perturbations and XOR-dense regions that degrade SAT solver performance. We contend that the modeling of the miter is as critical as the SAT solver itself. To this end, we introduce a miter-aware mapping framework that strategically formulates the problem before solving. By constructing a LUT-based miter -- instead of a traditional, flat netlist -- our approach preserves critical structural correspondence between the two designs while making high-level logic relations explicit. Our framework uniquely integrates three techniques: equivalence-preserving mapping to structurally align the two circuits, Gaussian-guided XOR modeling to algebraically simplify dense arithmetic, and solver-oriented LUT selection to generate a representation optimized for efficient SAT reasoning. Evaluated on comprehensive datasets, our method achieves up to a \textbf{92.1\%} reduction across state-of-the-art SAT solvers. This demonstrates that a solver-aware modeling paradigm, which unifies structural mapping with SAT reasoning, can fundamentally enhance LEC efficiency.

Problem

• Logic Equivalence Checking
• SAT solver
• structural perturbations
• XOR-dense regions
• miter

Innovation

• miter-aware mapping
• LUT-based miter
• logic equivalence checking
• Gaussian-guided XOR modeling
• solver-oriented LUT selection