🤖 AI Summary
External-memory BDD tool Adiar suffers from severe performance bottlenecks on medium-scale BDDs due to expensive initialization of redundant external data structures.
Method: We propose a level-aware memory demand prediction technique that formally establishes the correspondence between auxiliary data structures in BDD operations and graph cuts under level constraints. Leveraging this insight, we derive tight upper bounds on cut sizes for each operation and dynamically select optimal in-memory versus external-memory strategies. Our approach integrates graph-theoretic modeling, structural analysis of BDD levels, and rigorous theoretical bounding, and is embedded into Adiar’s runtime decision engine.
Contribution/Results: Experiments demonstrate an average 86.1% reduction in computation time for medium-scale BDDs (median reduction: 89.7%). In hardware circuit equivalence verification, individual instances accelerate by up to 52 hours, achieving speedups as high as 99.9%.
📝 Abstract
The BDD package Adiar manipulates Binary Decision Diagrams (BDDs) in external memory. This enables handling big BDDs, but the performance suffers when dealing with moderate-sized BDDs. This is mostly due to initializing expensive external memory data structures, even if their contents can fit entirely inside internal memory. The contents of these auxiliary data structures always correspond to a graph cut in an input or output BDD. Specifically, these cuts respect the levels of the BDD. We formalise the shape of these cuts and prove sound upper bounds on their maximum size for each BDD operation. We have implemented these upper bounds within Adiar. With these bounds, it can predict whether a faster internal memory variant of the auxiliary data structures can be used. In practice, this improves Adiar's running time across the board. Specifically for the moderate-sized BDDs, this results in an average reduction of the computation time by 86.1% (median of 89.7%). In some cases, the difference is even 99.9%. When checking equivalence of hardware circuits from the EPFL Benchmark Suite, for one of the instances the time was decreased by 52 hours.
