π€ AI Summary
High-Level Synthesis (HLS) tools impose stringent structural constraints on C code, and manual code refactoring is labor-intensive and error-prone.
Method: This paper proposes the first LLM-driven iterative HLS code refactoring framework, integrating systematic prompt engineering, feedback-guided multi-round rewriting, and modular hierarchical decomposition to enable bottom-up, semantics-preserving automatic refactoring of complex algorithms.
Contribution/Results: By deeply embedding large language models into the HLS workflow, the framework achieves end-to-end translation from generic C code to HLS-ready code. Evaluated on three cryptographic algorithms, one hash function, five NIST randomness tests, and QuickSort, it demonstrates superior efficacy: the complexity of generated HLS code exceeds that of existing LLM-based Verilog synthesis approaches by one to two orders of magnitude, significantly narrowing the semantic and structural gap between software and hardware design.
π Abstract
High-Level Synthesis (HLS) tools offer rapid hardware design from C code, but their compatibility is limited by code constructs. This paper investigates Large Language Models (LLMs) for automatically refactoring C code into HLS-compatible formats. We present a case study using an LLM to rewrite C code for NIST 800-22 randomness tests, a QuickSort algorithm, and AES-128 into HLS-synthesizable C. The LLM iteratively transforms the C code guided by the system prompt and toolβs feedback, implementing functions like streaming data and hardware-specific signals. With the hindsight obtained from the case study, we implement a fully automated framework to refactor C code into HLS-compatible formats using LLMs. To tackle complex designs, we implement a preprocessing step that breaks down the hierarchy in order to approach the problem in a divide-and-conquer bottom-up way. We validated our framework on three ciphers, one hash function, five NIST 800-22 randomness tests, and a QuickSort algorithm. Our results show a high success rate on benchmarks that are orders of magnitude more complex than what has been achieved generating Verilog with LLMs.