Synapse: Virtualizing Match Tables in Programmable Hardware

2025-05-17

AI Summary

To address the rigidity of match-table resources in programmable network hardware—particularly their inability to adapt dynamically to fluctuating traffic patterns and heterogeneous rule sets—this paper proposes the Virtual Match-Table (VMT) architecture. VMT introduces a novel, virtual-memory-inspired abstraction for match tables, integrating on-chip TCAM with off-chip DRAM in a hybrid storage hierarchy, augmented by traffic-aware sharding and millisecond-scale dynamic scheduling. This enables runtime elastic scaling of logical match tables and on-demand allocation of physical resources. Evaluated on an FPGA prototype, VMT supports dynamic insertion and deletion of over one million rules at line rate, achieves near-linear power consumption growth with query热度, and improves resource utilization by 3.2×. The architecture significantly enhances hardware adaptability and energy efficiency across diverse networking scenarios.

Technology Category

• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Routing
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

Efficient network packet processing increasingly demands dynamic, adaptive, and run-time resizable match table allocation to handle the diverse and heterogeneous nature of traffic patterns and rule sets. Achieving this flexibility at high performance in hardware is challenging, as fixed resource constraints and architectural limitations have traditionally restricted such adaptability. In this paper, we introduce Synapse, an extension to programmable data plane architectures that incorporates the Virtual Matching Table (VMT) framework, drawing inspiration from virtual memory systems in Operating Systems (OSs), but specifically tailored to network processing. This abstraction layer allows logical tables to be elastic, enabling dynamic and efficient match table allocation at runtime. Our design features a hybrid memory system, leveraging on-chip associative memories for fast matching of the most popular rules and off-chip addressable memory for scalable and cost-effective storage. Furthermore, by employing a sharding mechanism across physical match tables, Synapse ensures that the power required per key match remains bounded and proportional to the key distribution and the size of the involved shard. To address the challenge of dynamic allocation, we formulate and solve an optimization problem that dynamically allocates physical match tables to logical tables based on pipeline usage and traffic characteristics at the millisecond scale. We prototype our design on FPGA and develop a simulator to evaluate the performance, demonstrating its effectiveness and scalability.

Problem

• Dynamic match table allocation for network packet processing
• Overcoming hardware constraints for adaptable table virtualization
• Optimizing physical table allocation based on traffic patterns

Innovation

• Virtual Matching Table framework for dynamic allocation
• Hybrid memory system combining on-chip and off-chip storage
• Sharding mechanism for bounded power per key match