High-Performance ARM-on-ARM Virtualization for Multicore SystemC-TLM-Based Virtual Platforms

2025-05-19

AI Summary

To address the performance bottleneck of traditional instruction-set simulators (ISS) in SoC hardware-software co-verification, this paper proposes a high-performance ARM-on-ARM virtualization approach. It integrates Linux KVM hardware virtualization with SystemC-TLM modeling on an ARM host to construct a bare-metal-level virtual platform natively supporting multi-core target software execution. The key contribution is the first seamless integration of the KVM hypervisor driver with a SystemC-TLM CPU model—requiring no modifications to the host environment or target software and enabling out-of-the-box multi-core simulation. Experimental evaluation demonstrates that, under compute-intensive workloads, the proposed platform achieves an average 10× speedup over conventional ISS, with peak improvements exceeding 100× on certain benchmarks. This advancement significantly enhances the efficiency of SoC development and verification.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Simulating Human Behavior
• Data Mining & Knowledge Management: Scalability, Parallel & Distributed Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• Security and Privacy: Large-scale security measurements
• User Modeling, Personalization and Recommendation: User modeling and simulation for interactive and conversational systems

Abstract

The increasing complexity of hardware and software requires advanced development and test methodologies for modern systems on chips. This paper presents a novel approach to ARM-on-ARM virtualization within SystemC-based simulators using Linux's KVM to achieve high-performance simulation. By running target software natively on ARM-based hosts with hardware-based virtualization extensions, our method eliminates the need for instruction-set simulators, which significantly improves performance. We present a multicore SystemC-TLM-based CPU model that can be used as a drop-in replacement for an instruction-set simulator. It places no special requirements on the host system, making it compatible with various environments. Benchmark results show that our ARM-on-ARM-based virtual platform achieves up to 10 x speedup over traditional instruction-set-simulator-based models on compute-intensive workloads. Depending on the benchmark, speedups increase to more than 100 x.

Problem

• Enabling high-performance ARM virtualization in SystemC simulators
• Eliminating instruction-set simulators for faster ARM simulation
• Providing multicore SystemC-TLM CPU model for compatibility

Innovation

• ARM-on-ARM virtualization using KVM
• Multicore SystemC-TLM CPU model
• Hardware-based virtualization extensions