๐ค AI Summary
Neutral-atom quantum computers offer scalability and dynamic reconfigurability, yet existing compilation methods suffer from poor efficiency on large-scale circuits and fail to fully exploit hardware flexibility. To address this, we propose a physics-aware compilation framework. Our method introduces: (i) a novel hardware-aware plane partitioning strategy grounded in atomic mobility constraints and the operational characteristics of acousto-optic deflectors (AODs) and spatial light modulators (SLMs); (ii) a circuit partitioning algorithm enabling cross-region parallel execution while preserving gate fidelity; and (iii) an integrated optimization combining physical modeling, hardware-aware resource allocation, an enhanced KernighanโLin graph partitioning scheme, and architecture-specific adaptation to neutral-atom arrays. Evaluated on array sizes ranging from 16ร16 to 64ร64, our framework achieves up to 78.5ร compilation speedup over state-of-the-art approaches, with circuit quality matching or exceeding SOTA. Crucially, the speedup scales favorably with increasing problem size.
๐ Abstract
Neutral atom quantum computers are one of the most promising quantum architectures, offering advantages in scalability, dynamic reconfigurability, and potential for large-scale implementations. These characteristics create unique compilation challenges, especially regarding compilation efficiency while adapting to hardware flexibility. However, existing methods encounter significant performance bottlenecks at scale, hindering practical applications. We propose Physics-Aware Compilation (PAC), a method that improves compilation efficiency while preserving the inherent flexibility of neutral atom systems. PAC introduces physics-aware hardware plane partitioning that strategically allocates hardware resources based on physical device characteristics like AOD and SLM trap properties and qubit mobility constraints. Additionally, it implements parallel quantum circuit division with an improved Kernighan-Lin algorithm that enables simultaneous execution across independent regions while maintaining circuit fidelity. Our experimental evaluation compares PAC with state-of-the-art methods across increasingly larger array sizes ranging from 16x16 to 64x64 qubits. Results demonstrate that PAC achieves up to 78.5x speedup on 16x16 arrays while maintaining comparable circuit quality. PAC's compilation efficiency advantage increases with system scale, demonstrating scalability for practical quantum applications on larger arrays. PAC explores a viable path for practical applications of neutral atom quantum computers by effectively addressing the tension between compilation efficiency and hardware flexibility.