Assessing the Performance of Analog Training for Transfer Learning

2025-05-16

AI Summary

Device nonlinearity, switching asymmetry, and inter-cell variability in analog in-memory computing (AiMC) hardware severely degrade transfer learning performance. Method: This paper proposes c-TTv2, a novel training algorithm featuring a “chopped” weight update mechanism—first of its kind—that eliminates reliance on highly symmetric or high-precision bidirectional devices. Contribution/Results: c-TTv2 significantly enhances robustness against weight transmission noise, symmetry-point shift, and device variation. Evaluated via transfer learning on Swin-ViT using a CIFAR-100 subset, it achieves near-digital-training accuracy under realistic non-ideal AiMC conditions—error increase <1.2%. This work provides the first systematic validation of effective and stable fine-tuning for complex vision Transformer models on analog hardware. It establishes a scalable, low-overhead paradigm for analog-domain training tailored to edge AI applications.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Adversarial Attacks & Robustness
• Cognitive Modeling & Cognitive Systems: Analogy

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Security and Privacy: Security and privacy of machine learning and AI applications

Abstract

Analog in-memory computing is a next-generation computing paradigm that promises fast, parallel, and energy-efficient deep learning training and transfer learning (TL). However, achieving this promise has remained elusive due to a lack of suitable training algorithms. Analog memory devices exhibit asymmetric and non-linear switching behavior in addition to device-to-device variation, meaning that most, if not all, of the current off-the-shelf training algorithms cannot achieve good training outcomes. Also, recently introduced algorithms have enjoyed limited attention, as they require bi-directionally switching devices of unrealistically high symmetry and precision and are highly sensitive. A new algorithm chopped TTv2 (c-TTv2), has been introduced, which leverages the chopped technique to address many of the challenges mentioned above. In this paper, we assess the performance of the c-TTv2 algorithm for analog TL using a Swin-ViT model on a subset of the CIFAR100 dataset. We also investigate the robustness of our algorithm to changes in some device specifications, including weight transfer noise, symmetry point skew, and symmetry point variability

Problem

• Analog in-memory computing lacks suitable training algorithms
• Existing algorithms fail due to device asymmetry and variability
• Proposing c-TTv2 algorithm for robust analog transfer learning

Innovation

• Analog in-memory computing for energy-efficient transfer learning
• Chopped TTv2 algorithm addresses device non-linearity
• Swin-ViT model tested on CIFAR100 dataset