Problem
Research questions and friction points this paper is trying to address.
security assertions
RISC-V processors
hardware security verification
signal hallucination
model updates
AutoTrans: AI-Assisted Automatic Translation of Security Assertions for RISC-V Processors
🤖 AI Summary
为解决RISC-V处理器安全断言手动翻译耗时问题，提出AutoTrans框架，利用正则表达式提取信号、模板生成提示和形式验证方法，实现高效自动翻译。
📝 Abstract
Reusing a set of verified security assertions across RISC-V processor targets remains one of the most expensive bottlenecks in hardware security verification. Manual translation takes hours per assertion. Raw LLM translation is fast but unreliable, introducing signal hallucination, where the model invents port names absent from the target RTL and produces outputs that may vary across model updates or even within the same model version. This paper presents AutoTrans, an automated framework that addresses the above shortcomings. First, a new lightweight Regular Expression-based System Verilog signal extractor is proposed to identify the signals for generating security assertions. This step is necessary to prevent signal hallucination. Second, a template is introduced to create prompt and pinned inference parameters that guarantee a byte-identical prompt assembly on every run, making the pipeline output resilient to model updates. Moreover, the introduced template for LLM prompting is capable of generating security assertions from English-only security descriptions of RISC-V processors, with no manual authoring. Third, a formal verification process (JasperGold FPV) is integrated, which guarantees that the generated security assertions verify the security of the RISC-V processor rather than silently entering the result set. The workflow is applied on Deepseek V4 to translate security assertions from one RISC-V to another (e.g., for IBEX from NS31A RISC-V). The experiment shows that AutoTrans achieves 78\% Auto Translation Acceptance Rate (TAR) automatically and without human intervention and 100\% Final TAR after refinement by humans.
Innovation
Methods, ideas, or system contributions that make the work stand out.
Regular Expression-based Signal Extractor
Template for LLM Prompting
Formal Verification Integration
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