Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS

2025-05-15

AI Summary

Existing end-to-end open-source EDA toolchains lack the maturity to support industrial-grade, Linux-capable SoC design. Method: This work presents the first fully open-source, tapeout-ready 64-bit RISC-V SoC fabricated in IHP’s 130 nm BiCMOS process, integrating a custom CPU core, DRAM controller, and full-stack I/O peripherals—including USB, video, and chip-to-chip (C2C) interfaces. Contribution/Results: The 34 mm² die operates at 62–102 MHz with an energy efficiency of 18.9 DP MFLOP/s/W. It constitutes the first large-scale SoC-level validation of a complete open-source EDA flow, significantly improving timing closure, area utilization, and resource efficiency for Yosys synthesis and OpenROAD place-and-route under advanced nodes. Compared to state-of-the-art open-source flows, it achieves 1.6×–2.3× improvements in both synthesis performance and area efficiency—establishing a critical reference paradigm for open hardware scaling to system-level applications.

Technology Category

• Machine Learning: Hardware-aware ML
• Humans and AI: Other Foundations of Human Computation & AI
• Computer Vision: Computational Photography, Image & Video Synthesis

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Security and Privacy: Large-scale security measurements
• Responsible Web: Data and user privacy-enhancing technologies for the Web

Abstract

End-to-end open-source electronic design automation (OSEDA) enables a collaborative approach to chip design conducive to supply chain diversification and zero-trust step-by-step design verification. However, existing end-to-end OSEDA flows have mostly been demonstrated on small designs and have not yet enabled large, industry-grade chips such as Linux-capable systems-on-chip (SoCs). This work presents Basilisk, the largest end-to-end open-source SoC to date. Basilisk's 34 mm2, 2.7 MGE design features a 64-bit Linux-capable RISC-V core, a lightweight 124 MB/s DRAM controller, and extensive IO, including a USB 1.1 host, a video output, and a fully digital 62 Mb/s chip-to-chip (C2C) link. We implement Basilisk in IHP's open 130 nm BiCMOS technology, significantly improving on the state-of-the-art (SoA) OSEDA flow. Our enhancements of the Yosys-based synthesis flow improve design timing and area by 2.3x and 1.6x, respectively, while consuming significantly less system resources. By tuning OpenROAD place and route (P&R) to our design and technology, we decrease the die size by 12%. The fabricated Basilisk chip reaches 62 MHz at its nominal 1.2 V core voltage and up to 102 MHz at 1.64 V. It achieves a peak energy efficiency of 18.9 DP MFLOP/s/W at 0.88 V.

Problem

• Develops a large Linux-capable RISC-V SoC using open-source tools
• Enhances OSEDA flow for better timing, area, and resource efficiency
• Demonstrates scalable open-source chip design for industry-grade applications

Innovation

• Largest end-to-end open-source RISC-V SoC
• Enhanced Yosys synthesis for better performance
• Optimized OpenROAD P&R reducing die size