Scalable 28nm IC implementation of coupled oscillator network featuring tunable topology and complexity

2025-05-15

AI Summary

Large-scale coupled oscillator networks—such as power grids and neuromorphic systems—face severe computational bottlenecks in simulation due to high arithmetic intensity and hardware inflexibility. To address this, we present a 28 nm reconfigurable on-chip oscillator network chip. Our approach introduces a clustered phase-locked loop (PLL) architecture, with each cluster integrating seven programmable oscillators, co-designed with an embedded RISC-V coprocessor to enable runtime reconfiguration of both network topology and complexity—the first such capability demonstrated in hardware. The chip incorporates custom analog coupling circuits and a brain-inspired on-chip interconnect fabric, and has been silicon-verified for simulations involving hundreds of oscillators. Measurements show two orders-of-magnitude lower power consumption compared to pure digital simulation, significantly improving energy efficiency and adaptability for analog computing and dynamic modeling of critical infrastructure. This work establishes a new paradigm for hardware-accelerated analog computation.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Analogy
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Social Networks and Social Media: Computational social science
• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments

Abstract

Integrated circuit implementations of coupled oscillator networks have recently gained increased attention. The focus is usually on using these networks for analogue computing, for example for solving computational optimization tasks. For use within analog computing, these networks are run close to critical dynamics. On the other hand, such networks are also used as an analogy of transport networks such as electrical power grids to answer the question of how exactly such critical dynamic states can be avoided. However, simulating large network of coupled oscillators is computationally intensive, with specifc regards to electronic ones. We have developed an integrated circuit using integrated Phase-Locked Loop (PLL) with modifications, that allows to flexibly vary the topology as well as a complexity parameter of the network during operation. The proposed architecture, inspired by the brain, employs a clustered architecture, with each cluster containing 7 PLLs featuring programmable coupling mechanisms. Additionally, the inclusion of a RISC-V processor enables future algorithmic implementations. Thus, we provide a practical alternative for large-scale network simulations both in the field of analog computing and transport network stability research.

Problem

• Implement scalable 28nm IC for tunable coupled oscillator networks
• Enable flexible topology and complexity adjustment during operation
• Provide efficient alternative for large-scale analog computing simulations

Innovation

• 28nm IC with tunable oscillator network topology
• Modified PLLs enable flexible complexity adjustment
• Clustered architecture inspired by brain connectivity