OTTER - Two Transistor - One RRAM Architecture for Reliable In-Memory-Computing in 28 nm CMOS Technology

2026-09-08

AI Summary

本文提出了一种28纳米CMOS技术下的OTTER架构，采用2T1R设计解决可靠内存计算问题，通过实验与模拟优化晶体管尺寸，并展示了其在多级导电调节及CIM MAC操作中的应用。

Abstract

This work presents OTTER, a 28 nm CMOS platform co-integrated with TaOx-based valence-change mechanism (VCM) RRAM, demonstrating a two-transistor-one-memristive-device (2T1R) architecture for reliable in-memory computing. The 2T1R cell combines a low-drive-current (LD) transistor and a high-drive-current (HD) transistor in parallel, providing dedicated bias paths for SET programming and RESET operation, respectively. Through systematic experimental and simulated comparison of various transistor-pairing configurations using the physical compact model JART VCM Rth, design guidelines for transistor sizing are derived, establishing the minimum RESET transistor W/L required for complete RESET as a function of the SET current compliance. The 2T1R cell is further characterized under pulse-based programming, demonstrating multilevel analog conductance tuning with narrow, well separated conductance states across six programmable levels. An analog content-addressable memory (aCAM) design based on the same 2T1R cell is additionally analyzed at the circuit level, evaluating trade-offs between top- and bottom-connected RRAM comparator configurations. A hardware implementation of compute-in-memory (CIM) multiply-and-accumulate (MAC) operations is further demonstrated on a 15 x 15 2T1R crossbar array.

Problem

• in-memory computing
• 2T1R architecture
• reliable computation
• 28 nm CMOS
• RRAM

Innovation

• 2T1R architecture
• in-memory computing
• TaOx-based RRAM
• multilevel analog conductance tuning
• compute-in-memory (CIM)