Differentiable Partitioning with Placement and Hybrid Bonding Terminal Awareness for Optimized 3D Placement

2026-09-06

AI Summary

本文提出了一种可微分分区框架，通过基于梯度的优化方法解决3D-ICs中层分配问题，减少了芯片间半周长线长，提高了混合键合终端区域的布局效率。

Abstract

Research on 3D-ICs physical design has expanded rapidly in recent years. Hybrid bonding-enabled 3D integrated circuits (3D-ICs) offer substantial benefits in interconnect scaling and system integration, yet tier assignment remains challenging because it jointly determines 3D wirelength and hybrid bonding terminal (HBT) assignment. This paper presents a differentiable partitioning framework that directly optimizes placement-aware tier assignment for 3D-ICs through gradient-based optimization. Discrete tier assignment is relaxed to continuous probabilities, and a Dual-Max 3D wirelength model is introduced to capture per-tier half-perimeter wirelength (HPWL). In addition, a terminal-aware cutsize penalty selectively suppresses cross-die nets in HBT-congested regions, and a local balance constraint enforces grid-cell density equilibrium across tiers. Experimental results on OpenROAD benchmarks show that our method reduces D2D HPWL by 2.0% on average over two min-cut baselines and by 12.1% over the state-of-the-art 3D placer. We open-source our partition code with 3D placement flow to support reproducibility.

Problem

• 3D-ICs
• tier assignment
• 3D wirelength
• hybrid bonding terminal
• physical design

Innovation

• differentiable partitioning
• placement-aware tier assignment
• gradient-based optimization
• hybrid bonding terminal
• local balance constraint