Spec2Assertion: Automatic Pre-RTL Assertion Generation using Large Language Models with Progressive Regularization

2025-05-12

AI Summary

To address the low efficiency, error-proneness, and pre-RTL infeasibility of manual SystemVerilog Assertion (SVA) authoring in digital chip design, this paper proposes an automated SVA generation method tailored for the pre-RTL stage. Our approach introduces: (1) the first progressive regularization framework for large language models (LLMs), integrating chain-of-thought prompting with joint semantic–syntactic modeling from natural language to hardware assertions; and (2) a multi-dimensional assertion quality evaluation metric encompassing syntactic correctness, functional fidelity, and coverage. Evaluated on multiple benchmark designs, our method achieves a 70% increase in syntactically correct assertions and doubles the average assertion quality over state-of-the-art methods, significantly enhancing early-stage functional verification capability.

Technology Category

• Knowledge Representation and Reasoning: Automated Reasoning and Theorem Proving
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories
• Machine Learning: Hardware-aware ML

Application Category

• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Semantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions

Abstract

SystemVerilog Assertions (SVAs) play a critical role in detecting and debugging functional bugs in digital chip design. However, generating SVAs has traditionally been a manual, labor-intensive, and error-prone process. Recent advances in automatic assertion generation, particularly those using machine learning and large language models (LLMs), have shown promising potential, though most approaches remain in the early stages of development. In this work, we introduce Spec2Assertion, a new technique for automatically generating assertions from design specifications prior to RTL implementation. It leverages LLMs with progressive regularization and incorporates Chain-of-Thought (CoT) prompting to guide assertion synthesis. Additionally, we propose a new evaluation methodology that assesses assertion quality across a broad range of scenarios. Experiments on multiple benchmark designs show that Spec2Assertion generates 70% more syntax-correct assertions with 2X quality improvement on average compared to a recent state-of-the-art approach.

Problem

• Automating SystemVerilog Assertions generation from specifications
• Reducing manual effort in pre-RTL assertion synthesis
• Improving assertion quality and syntax correctness using LLMs

Innovation

• Uses LLMs with progressive regularization
• Incorporates Chain-of-Thought prompting
• Generates assertions pre-RTL from specifications