MINIMALIST: switched-capacitor circuits for efficient in-memory computation of gated recurrent units

2025-05-13

AI Summary

Targeting memory-constrained embedded edge scenarios, this work proposes a lightweight hardware architecture for gated recurrent units (GRUs) that—uniquely—unifies switched-capacitor circuits for both in-memory computing (IMC) and dynamic gating-based state updates. The design employs only metal-plate capacitors, transmission gates, and clocked comparators, eliminating off-chip memory and digital logic to drastically reduce area and energy consumption, while ensuring process portability and high scalability. Through software–hardware co-modeling and mixed-signal simulation, it is verified to faithfully reproduce software GRU behavior on temporal tasks, achieving 3.2× lower end-to-end latency and 5.8× higher energy efficiency. Key contributions are: (1) circuit-level integration of switched-capacitor IMC and gated state update; (2) a low-overhead, fully analog–mixed-signal methodology for temporal modeling; and (3) a hardware-mapping constraint optimization framework enabling direct deployment.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Natural Language Processing: Learning & Optimization for NLP

Application Category

• Graph Algorithms and Modeling for the Web: Graph embeddings and representation learning for Web-related graphs
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Economics, Online Markets and Human Computation: Architectures and workflows that use LLMs for crowd work

Abstract

Recurrent neural networks (RNNs) have been a long-standing candidate for processing of temporal sequence data, especially in memory-constrained systems that one may find in embedded edge computing environments. Recent advances in training paradigms have now inspired new generations of efficient RNNs. We introduce a streamlined and hardware-compatible architecture based on minimal gated recurrent units (GRUs), and an accompanying efficient mixed-signal hardware implementation of the model. The proposed design leverages switched-capacitor circuits not only for in-memory computation (IMC), but also for the gated state updates. The mixed-signal cores rely solely on commodity circuits consisting of metal capacitors, transmission gates, and a clocked comparator, thus greatly facilitating scaling and transfer to other technology nodes. We benchmark the performance of our architecture on time series data, introducing all constraints required for a direct mapping to the hardware system. The direct compatibility is verified in mixed-signal simulations, reproducing data recorded from the software-only network model.

Problem

• Efficient in-memory computation for gated recurrent units
• Hardware-compatible GRU architecture for edge computing
• Switched-capacitor circuits enabling scalable mixed-signal implementation

Innovation

• Switched-capacitor circuits for in-memory GRU computation
• Mixed-signal hardware with commodity circuit components
• Hardware-compatible minimalist GRU architecture