Flexing RISC-V Instruction Subset Processors (RISPs) to Extreme Edge

2025-05-07

AI Summary

To address the stringent requirements of extreme-edge computing—namely energy efficiency, cost-effectiveness, adaptability, and sustainability—this paper proposes an automated framework for generating instruction-set-customized RISC-V processors (RISPs). Our method introduces an “instruction-as-module” design paradigm, wherein each RISC-V instruction is mapped to a pre-verified hardware module, enabling co-generation and co-verification to drastically reduce development time and verification overhead. The framework integrates RISC-V instruction-set pruning, modular hardware synthesis, flexible integrated circuit (FlexIC) physical design and tape-out, and Embench benchmarking. Experimental results demonstrate that, compared to full-featured RISC-V processors, RISPs achieve average reductions of 30% in both power consumption and silicon area. Against the smallest existing 32-bit RISC-V core, Serv, RISPs deliver approximately 30× higher energy efficiency, along with 21% smaller area and 26% lower power consumption.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Computational Photography, Image & Video Synthesis
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding

Application Category

• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments

Abstract

This paper presents a methodology for automatically generating processors that support a subset of the RISC-V instruction set for a new class of applications at Extreme Edge. The electronics used in extreme edge applications must be power-efficient, but also provide additional qualities, such as low cost, conformability, comfort and sustainability. Flexible electronics, rather than silicon-based electronics, will be capable of meeting these qualities. For this purpose, we propose a methodology to generate RISPs (RISC-V instruction subset processors) customised to extreme edge applications and to implement them as flexible integrated circuits (FlexICs). The methodology is unique in the sense that verification is an integral part of design. The RISP methodology treats each instruction in the ISA as a discrete, fully functional, pre-verified hardware block. It automatically builds a custom processor by stitching together the hardware blocks of the instructions required by an application or a set of applications in a specific domain. This approach significantly reduces the processor verification and its time-to-market. We generate RISPs using this methodology for three extreme edge applications, and embedded applications from the Embench benchmark suite, synthesize them as FlexICs, and compare their power, performance and area to the baselines. Our results show that RISPs generated using this methodology achieve, on average, 30% reductions in power and area compared to a RISC-V processor supporting the full instruction set when synthesized, and are nearly 30 times more energy efficient with respect to Serv - the world's smallest 32-bit RISC-V processor. In addition, the full physical implementation of RISPs show up to 21% and 26% less area and power than Serv.

Problem

• Automate RISC-V subset processors for extreme edge applications
• Enable power-efficient flexible electronics with low cost
• Reduce verification time and accelerate processor time-to-market

Innovation

• Automatically generates RISC-V subset processors
• Uses pre-verified hardware blocks per instruction
• Implements processors as flexible integrated circuits