Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU

2025-05-06

AI Summary

RISC-V GPUs lack native hardware support for warp-level primitives essential to modern GPU programming. To address this, this work pioneers a holistic hardware–software co-design approach: (1) a custom hardware warp scheduler is designed to accelerate warp-level operations, and (2) a lightweight software emulation layer is implemented in the LLVM compiler infrastructure. Evaluated on the open-source Vortex GPU architecture, both approaches are rigorously compared across performance, silicon area, and software compatibility. The hardware solution achieves up to 4× geomean IPC improvement on microbenchmarks; the software solution delivers full functional coverage while significantly reducing area overhead. This study establishes the practical feasibility and scalability limits of warp-level abstractions in RISC-V GPU designs, providing foundational insights and empirical guidance for developing high-performance, open-source GPU architectures supporting modern parallel programming models.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Low Level & Physics-based Vision
• Humans and AI: Game Design — Virtual Humans, NPCs and Autonomous Characters

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• Responsible Web: Data and user privacy-enhancing technologies for the Web

Abstract

RISC-V GPUs present a promising path for supporting GPU applications. Traditionally, GPUs achieve high efficiency through the SPMD (Single Program Multiple Data) programming model. However, modern GPU programming increasingly relies on warp-level features, which diverge from the conventional SPMD paradigm. In this paper, we explore how RISC-V GPUs can support these warp-level features both through hardware implementation and via software-only approaches. Our evaluation shows that a hardware implementation achieves up to 4 times geomean IPC speedup in microbenchmarks, while software-based solutions provide a viable alternative for area-constrained scenarios.

Problem

• Supporting warp-level features in RISC-V GPUs
• Comparing hardware vs. software implementation approaches
• Evaluating performance trade-offs for SPMD divergence

Innovation

• Hardware implementation boosts IPC speedup significantly
• Software solutions suit area-constrained scenarios effectively
• RISC-V GPU supports warp-level features innovatively