DeCo: Defect-Aware Modeling with Contrasting Matching for Optimizing Task Assignment in Online IC Testing

2025-05-01

AI Summary

To address inefficient task assignment and misalignment between defect identification and engineer matching in semiconductor IC online testing, this paper proposes a defect-aware intelligent dispatching method. The approach constructs a defect-aware graph by integrating defect features, historical failure modes, and engineer expertise, enabling joint representation learning of human-task collaboration. It introduces a novel multi-granularity (local/global) embedding and dynamic matching mechanism based on graph neural networks and contrastive learning—first achieving unified modeling of engineer skills, workload, and defect semantics. The method exhibits strong generalization even under scarce defect data, balancing dispatching success rate and workload fairness. Evaluated on a real-world industrial dataset, it achieves over 80% task resolution success rate, significantly improving test efficiency and reducing misjudgment costs.

Technology Category

• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Search and Optimization: Distributed Search
• Machine Learning: Hardware-aware ML

Application Category

• Graph Algorithms and Modeling for the Web: Graph embeddings and representation learning for Web-related graphs
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Economics, Online Markets and Human Computation: Trust and reliance of crowd workers and data experts on GenAI

Abstract

In the semiconductor industry, integrated circuit (IC) processes play a vital role, as the rising complexity and market expectations necessitate improvements in yield. Identifying IC defects and assigning IC testing tasks to the right engineers improves efficiency and reduces losses. While current studies emphasize fault localization or defect classification, they overlook the integration of defect characteristics, historical failures, and the insights from engineer expertise, which restrains their effectiveness in improving IC handling. To leverage AI for these challenges, we propose DeCo, an innovative approach for optimizing task assignment in IC testing. DeCo constructs a novel defect-aware graph from IC testing reports, capturing co-failure relationships to enhance defect differentiation, even with scarce defect data. Additionally, it formulates defect-aware representations for engineers and tasks, reinforced by local and global structure modeling on the defect-aware graph. Finally, a contrasting-based assignment mechanism pairs testing tasks with QA engineers by considering their skill level and current workload, thus promoting an equitable and efficient job dispatch. Experiments on a real-world dataset demonstrate that DeCo achieves the highest task-handling success rates in different scenarios, exceeding 80%, while also maintaining balanced workloads on both scarce or expanded defect data. Moreover, case studies reveal that DeCo can assign tasks to potentially capable engineers, even for their unfamiliar defects, highlighting its potential as an AI-driven solution for the real-world IC failure analysis and task handling.

Problem

• Optimizing IC testing task assignment using defect-aware modeling
• Integrating defect characteristics and engineer expertise for efficiency
• Balancing workload and skill matching in semiconductor QA

Innovation

• Constructs defect-aware graph from IC testing reports
• Formulates defect-aware representations for engineers and tasks
• Uses contrasting-based assignment mechanism for task pairing