2T1R Regulated Memristor Conductance Control Array Architecture for Neuromorphic Computing using 28nm CMOS Technology

2025-05-19

AI Summary

Memristor crossbars for neuromorphic computing suffer from voltage division, virtual ground effects, and sneak-path current interference. To address these challenges, this work proposes a 2T1R (two-transistor–one-memristor) conductance-regulated memristor array architecture fabricated in 28 nm CMOS technology. The 2T1R cell enables controlled constant-current driving and precise analog conductance programming. Crucially, a novel two-terminal grounded configuration is introduced—fully eliminating sneak-path currents while simultaneously suppressing voltage division and virtual ground effects induced by interconnect resistance. Experimental results demonstrate substantial improvements in vector–matrix multiplication (VMM) accuracy and energy efficiency. The architecture achieves high stability and scalability, enabling a hardware prototype of brain-inspired computing arrays with robust performance at the circuit level.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Intelligent Robots: Multimodal Perception & Sensor Fusion

Application Category

• Responsible Web: Machine-in-the-loop, human agency and autonomy
• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• Security and Privacy: Privacy-enhancing technologies

Abstract

Memristors are promising devices for scalable and low power, in-memory computing to improve the energy efficiency of a rising computational demand. The crossbar array architecture with memristors is used for vector matrix multiplication (VMM) and acts as kernels in neuromorphic computing. The analog conductance control in a memristor is achieved by applying voltage or current through it. A basic 1T1R array is suitable to avoid sneak path issues but suffer from wire resistances, which affects the read and write procedures. A conductance control scheme with a regulated voltage source will improve the architecture and reduce the possible potential divider effects. A change in conductance is also possible with the provision of a regulated current source and measuring the voltage across the memristors. A regulated 2T1R memristor conductance control architecture is proposed in this work, which avoids the potential divider effect and virtual ground scenario in a regular crossbar scheme, as well as conductance control by passing a regulated current through memristors. The sneak path current is not allowed to pass by the provision of ground potential to both terminals of memristors.

Problem

• Improving memristor conductance control in neuromorphic computing
• Addressing wire resistance issues in 1T1R array architectures
• Eliminating sneak path currents in crossbar array designs

Innovation

• 2T1R memristor array for neuromorphic computing
• Regulated current source for conductance control
• Avoids sneak path and potential divider effects