STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration

2025-04-29

AI Summary

To address thermal bottlenecks, coefficient-of-thermal-expansion (CTE) mismatch, and degraded reliability induced by compact layouts in 2.5D heterogeneous integration, this paper proposes the first automated floorplanning methodology jointly optimizing thermal, mechanical stress, and interconnect objectives. Unlike conventional single-objective approaches, our method integrates finite element analysis (FEA) to co-model temperature distribution and stress fields, establishing a multi-objective协同 floorplanning framework that for the first time uncovers the coupling mechanism between thermal gradients and structural integrity. Experimental results demonstrate that, compared to a thermal-only optimization baseline, the proposed method reduces overall mechanical stress by 11%, decreases total interconnect wirelength by 11%, and incurs only a marginal temperature rise of 0.5°C—thereby significantly enhancing long-term system reliability.

Technology Category

• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Search and Optimization: Mixed Discrete/Continuous Search

Application Category

• Graph Algorithms and Modeling for the Web: Algorithms and analysis for heterogeneous, signed, attributed, multi-relational, temporal, higher-order, and annotated Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Web Mining and Content Analysis: Robustness and generalizability of Web mining methods

Abstract

Chiplet-based architectures and advanced packaging has emerged as transformative approaches in semiconductor design. While conventional physical design for 2.5D heterogeneous systems typically prioritizes wirelength reduction through tight chiplet packing, this strategy creates thermal bottlenecks and intensifies coefficient of thermal expansion (CTE) mismatches, compromising long-term reliability. Addressing these challenges requires holistic consideration of thermal performance, mechanical stress, and interconnect efficiency. We introduce STAMP-2.5D, the first automated floorplanning methodology that simultaneously optimizes these critical factors. Our approach employs finite element analysis to simulate temperature distributions and stress profiles across chiplet configurations while minimizing interconnect wirelength. Experimental results demonstrate that our thermal structural aware automated floorplanning approach reduces overall stress by 11% while maintaining excellent thermal performance with a negligible 0.5% temperature increase and simultaneously reducing total wirelength by 11% compared to temperature-only optimization. Additionally, we conduct an exploratory study on the effects of temperature gradients on structural integrity, providing crucial insights for reliability-conscious chiplet design. STAMP-2.5D establishes a robust platform for navigating critical trade-offs in advanced semiconductor packaging.

Problem

• Optimizes thermal performance and mechanical stress in 2.5D chiplet placement
• Reduces interconnect wirelength while addressing thermal expansion mismatches
• Balances reliability and efficiency in heterogeneous semiconductor packaging

Innovation

• Simultaneously optimizes thermal, stress, and wirelength
• Uses finite element analysis for temperature and stress
• Reduces stress and wirelength while maintaining thermal performance