Device-Algorithm Co-Design of Ferroelectric Compute-in-Memory In-Situ Annealer for Combinatorial Optimization Problems

2025-04-30

AI Summary

Traditional Ising annealers suffer from high VMV multiplication complexity (O(n²)), expensive exponential annealing factor computation, and prohibitive hardware costs when solving combinatorial optimization problems (COPs). To address these challenges, this work proposes an in-situ annealing architecture leveraging ferroelectric compute-in-memory (CIM). We introduce an incremental-E problem transformation that reduces Ising energy evaluation complexity to O(n); replace exponential annealing factors with fractional approximations; and, for the first time, implement tunable back-gate in-situ annealing on a dual-gate ferroelectric FET (DG-FeFET) crossbar array. Evaluated on a 3,000-node Max-Cut benchmark, our design achieves 1,503–1,716× lower energy consumption, 8.08–8.15× faster solution time, and an average success rate of 98%—a substantial improvement over the baseline’s 50%. These results mark a significant advance toward low-power, high-efficiency hardware for COP solving.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Satisfiability
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Systems and Infrastructure for Web, Mobile and WoT: Energy management for devices in mobile Web and WoT environments

Abstract

Combinatorial optimization problems (COPs) are crucial in many applications but are computationally demanding. Traditional Ising annealers address COPs by directly converting them into Ising models (known as direct-E transformation) and solving them through iterative annealing. However, these approaches require vector-matrix-vector (VMV) multiplications with a complexity of $O(n^2)$ for Ising energy computation and complex exponential annealing factor calculations during annealing process, thus significantly increasing hardware costs. In this work, we propose a ferroelectric compute-in-memory (CiM) in-situ annealer to overcome aforementioned challenges. The proposed device-algorithm co-design framework consists of (i) a novel transformation method (first to our known) that converts COPs into an innovative incremental-E form, which reduces the complexity of VMV multiplication from $O(n^2)$ to $O(n)$, and approximates exponential annealing factor with a much simplified fractional form; (ii) a double gate ferroelectric FET (DG FeFET)-based CiM crossbar that efficiently computes the in-situ incremental-E form by leveraging the unique structure of DG FeFETs; (iii) %When feasible solutions are detected, a CiM annealer that approaches the solutions of COPs via iterative incremental-E computations within a tunable back gate-based in-situ annealing flow. Evaluation results show that our proposed CiM annealer significantly reduces hardware overhead, reducing energy consumption by 1503/1716$ imes$ and time cost by 8.08/8.15$ imes$ in solving 3000-node Max-Cut problems compared to two state-of-the-art annealers. It also exhibits high solving efficiency, achieving a remarkable average success rate of 98%, whereas other annealers show only 50% given the same iteration counts.

Problem

• Reducing computational complexity of combinatorial optimization problems
• Overcoming hardware cost challenges in Ising annealers
• Enhancing efficiency and success rate in solving Max-Cut problems

Innovation

• Incremental-E form reduces VMV complexity to O(n)
• DG FeFET-based CiM crossbar enables efficient computation
• Simplified fractional form approximates exponential annealing factor