VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction

2025-04-27

AI Summary

Low automation in Verilog HDL debugging and insufficient exploration of large language models (LLMs) for this task motivate this work. We propose VeriDebugLoc-Type, a unified end-to-end LLM framework for Verilog bug localization and repair. It introduces, for the first time, a joint modeling mechanism combining contrastive embedding and guided correction, enabling simultaneous learning of bug detection patterns and repair strategies within a shared parameter space—departing from conventional decoupled debugging paradigms. The framework integrates contrastive learning–based embedding retrieval, instruction-tuned lightweight LLMs, and Verilog syntax–aware guided decoding. On standard benchmarks, VeriDebugLoc-Type achieves 64.7% top-1 bug repair accuracy (Acc1), outperforming open-source state-of-the-art by +11.3 points and GPT-3.5-turbo by +28.1 points. This establishes a scalable, high-accuracy paradigm for automated hardware design debugging.

Technology Category

• Machine Learning: Large Multimodal Models (LMMs)
• Knowledge Representation and Reasoning: Diagnosis and Abductive Reasoning
• Humans and AI: Human-in-the-loop Machine Learning

Application Category

• Search and Retrieval-Augmented AI: Search Tool Learning with LLM: Teaching LLMs to invoke search and make use of retrieved information
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs
• User Modeling, Personalization and Recommendation: Large Language Models (LLM) for user modeling and recommendation

Abstract

Large Language Models (LLMs) have demonstrated remarkable potential in debugging for various programming languages. However, the application of LLMs to Verilog debugging remains insufficiently explored. Here, we present VeriDebug, an approach that integrates contrastive representation and guided correction capabilities for automated Verilog debugging. Unlike existing methods, VeriDebug employs an embedding-based technique to accurately retrieve internal information, followed by bug-fixing. VeriDebug unifies Verilog bug detection and correction through a shared parameter space. By simultaneously learning bug patterns and fixes, it streamlines debugging via contrastive embedding and guided correction. Empirical results show the efficacy of VeriDebug in enhancing Verilog debugging. Our VeriDebugLoc, Type model achieves 64.7 accuracy in bug fixing (Acc1), a significant improvement from the existing open-source SOTAs 11.3. This performance not only outperforms open-source alternatives but also exceeds larger closed-source models like GPT-3.5-turbo (36.6), offering a more accurate alternative to conventional debugging methods.

Problem

• Developing a unified LLM for Verilog debugging
• Integrating contrastive embedding for accurate bug detection
• Enhancing bug-fixing accuracy via guided correction techniques

Innovation

• Uses contrastive embedding for accurate information retrieval
• Unifies bug detection and correction in shared space
• Combines guided correction with contrastive learning