EvolVE: Evolutionary Search for LLM-based Verilog Generation and Optimization

2026-01-26

AI Summary

This work addresses the inefficiency of traditional Verilog design flows, which heavily rely on expert intuition, and the limitations of current large language models that struggle to capture the rigorous logic and inherent concurrency of hardware due to constraints in training data and sequential reasoning. To overcome these challenges, the authors propose EvolVE, a novel framework that systematically evaluates diverse evolutionary strategies for RTL design. EvolVE integrates Monte Carlo Tree Search (MCTS) to enhance functional correctness, employs Idea-Guided Refinement (IGR) to optimize code quality, and introduces Structured Testbench Generation (STG) to accelerate the evolutionary process. The approach achieves state-of-the-art results with 98.1% and 92% accuracy on VerilogEval v2 and RTLLM v2, respectively, and outperforms competition-winning solutions on a newly introduced industrial-scale IC-RTL benchmark, reducing geometric mean PPA by 17% and achieving up to 66% reduction in a Huffman coding task.

Technology Category

• Machine Learning: Evolutionary Learning
• Search and Optimization: Evolutionary Computation
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language

Application Category

• Economics, Online Markets and Human Computation: Architectures and workflows that use LLMs for crowd work
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs

Abstract

Verilog's design cycle is inherently labor-intensive and necessitates extensive domain expertise. Although Large Language Models (LLMs) offer a promising pathway toward automation, their limited training data and intrinsic sequential reasoning fail to capture the strict formal logic and concurrency inherent in hardware systems. To overcome these barriers, we present EvolVE, the first framework to analyze multiple evolution strategies on chip design tasks, revealing that Monte Carlo Tree Search (MCTS) excels at maximizing functional correctness, while Idea-Guided Refinement (IGR) proves superior for optimization. We further leverage Structured Testbench Generation (STG) to accelerate the evolutionary process. To address the lack of complex optimization benchmarks, we introduce IC-RTL, targeting industry-scale problems derived from the National Integrated Circuit Contest. Evaluations establish EvolVE as the new state-of-the-art, achieving 98.1% on VerilogEval v2 and 92% on RTLLM v2. Furthermore, on the industry-scale IC-RTL suite, our framework surpasses reference implementations authored by contest participants, reducing the Power, Performance, Area (PPA) product by up to 66% in Huffman Coding and 17% in the geometric mean across all problems. The source code of the IC-RTL benchmark is available at https://github.com/weiber2002/ICRTL.

Problem

• Verilog generation
• Large Language Models
• hardware design automation
• functional correctness
• PPA optimization

Innovation

• Evolutionary Search
• LLM-based Verilog Generation
• Monte Carlo Tree Search
• Idea-Guided Refinement
• Structured Testbench Generation