RTeAAL Sim: Using Tensor Algebra to Represent and Accelerate RTL Simulation (Extended Version)

2026-01-26

AI Summary

RTL simulation on CPUs suffers from long compilation times, high instruction cache pressure, and front-end performance bottlenecks. This work presents the first formulation of RTL simulation as a sparse tensor algebra problem, wherein circuit structures are represented as tensors and simulation is executed using highly optimized tensor algebra kernels. This approach decouples simulation behavior from binary size, enabling direct leveraging of mature tensor optimization techniques to significantly reduce both compilation overhead and instruction cache pressure. A prototype implementation achieves runtime performance comparable to the highly optimized Verilator across diverse CPU architectures and instruction set architectures, demonstrating the effectiveness and generality of the proposed paradigm.

Technology Category

• Machine Learning: Matrix & Tensor Methods
• Search and Optimization: Sampling/Simulation-based Search
• Knowledge Representation and Reasoning: Computational Complexity of Reasoning

Application Category

• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs

Abstract

RTL simulation on CPUs remains a persistent bottleneck in hardware design. State-of-the-art simulators embed the circuit directly into the simulation binary, resulting in long compilation times and execution that is fundamentally CPU frontend-bound, with severe instruction-cache pressure. This work proposes RTeAAL Sim, which reformulates RTL simulation as a sparse tensor algebra problem. By representing RTL circuits as tensors and simulation as a sparse tensor algebra kernel, RTeAAL Sim decouples simulation behavior from binary size and makes RTL simulation amenable to well-studied tensor algebra optimizations. We demonstrate that a prototype of our tensor-based simulator, even with a subset of these optimizations, already mitigates the compilation overhead and frontend pressure and achieves performance competitive with the highly optimized Verilator simulator across multiple CPUs and ISAs.

Problem

• RTL simulation
• CPU bottleneck
• compilation overhead
• instruction-cache pressure
• frontend-bound execution

Innovation

• tensor algebra
• RTL simulation
• sparse tensors
• hardware simulation
• frontend-bound optimization