🤖 AI Summary
In multi-chip packages, wireless networks-on-chip (WNoCs) suffer from severe co-channel and inter-symbol interference, fundamentally limiting link density and data rate.
Method: This work pioneers the application of time-reversal (TR) techniques to near-field inter-chip wireless communication, proposing a spatio-temporal focusing-based interference mitigation framework. Leveraging full-wave electromagnetic modeling, near-field channel characterization, and low-sampling-rate TR filter optimization, it achieves high-fidelity channel matching and multipath energy focusing.
Results: Experiments demonstrate a 10× increase in per-link symbol rate, enabling parallel multi-link transmission with an aggregate throughput exceeding 100 Gb/s. Feasibility of TR at chip-scale under low sampling rates is experimentally validated. This approach breaks the conventional bandwidth and spatial reuse bottlenecks of WNoCs, establishing a new paradigm for high-density, high-speed wireless interconnects in multi-chip systems.
📝 Abstract
The concept of Wireless Network-on-Chip (WNoC) has emerged as a potential solution to address the escalating communication demands of modern computing systems due to its low-latency, versatility, and reconfigurability. However, for WNoC to fulfill its potential, it is essential to establish multiple high-speed wireless links across chips. Unfortunately, the compact and enclosed nature of computing packages introduces significant challenges in the form of Co-Channel Interference and Inter-Symbol Interference, which not only hinder the deployment of multiple spatial channels but also severely restrict the symbol rate of each individual channel. In this paper, we posit that Time Reversal (TR) could be effective in addressing both impairments in this static scenario thanks to its spatiotemporal focusing capabilities even in the near field. Through comprehensive full-wave simulations and bit error rate analysis in multiple scenarios and at multiple frequency bands, we provide evidence that TR can increase the symbol rate by an order of magnitude, enabling the deployment of multiple concurrent links and achieving aggregate speeds exceeding 100 Gb/s. Finally, we evaluate the impact of reducing the sampling rate of the TR filter on the achievable speeds, paving the way to practical TR-based wireless communications at the chip scale.